Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors: Satyanarayan Thakur

Abstract: With continued scaling of semiconductor technologies and growing complexity of integrated circuits, design failure and yield loss have emerged as major concerns in VLSI design and manufacturing. Traditional rule-based verification and post-silicon analysis techniques are no longer sufficient to handle the massive design space and variability introduced by advanced process nodes. Predictive analytics, driven by machine learning and data-driven models, offers a promising solution to anticipate design failures and predict manufacturing yield early in the design cycle. This paper presents a comprehensive review of predictive analytics techniques applied to design failure detection and yield prediction in VLSI systems. The study discusses data sources, modeling approaches, integration within electronic design automation (EDA) workflows, and practical challenges. Recent advances in deep learning, ensemble models, and hybrid physics-aware analytics are examined. The paper also highlights case studies and emerging trends that indicate how predictive analytics can significantly reduce design iterations, cost, and time-to-market. Finally, future research directions are outlined, emphasizing the role of explainable and adaptive analytics in next-generation chip design.

Keywords: Predictive analytics, design failure prediction, yield estimation, VLSI, machine learning, semiconductor manufacturing

Authors: Anirudh K. Chaube, Satish Kulkarni, Ravi Teja P

Abstract: Power, Performance, and Area (PPA) optimization has always been a central challenge in VLSI design and electronic design automation (EDA). As semiconductor technology scales into deep sub-micron and nanometer regimes, traditional heuristic-based optimization methods struggle to handle the increasing design complexity and conflicting objectives among power, performance, and silicon area. Recently, reinforcement learning (RL) has emerged as a promising paradigm for addressing such multi-objective optimization problems due to its ability to learn optimal strategies through interaction with complex environments. This paper presents a comprehensive review of reinforcement learning techniques applied to multi-objective PPA optimization across different stages of the VLSI design flow. We discuss fundamental RL concepts, formulation of PPA optimization as a multi-objective Markov decision process, commonly used reward models, and state-action representations. Furthermore, the paper surveys recent applications of RL in logic synthesis, placement, routing, and power management, highlighting both academic and industrial efforts. Challenges such as reward shaping, sample efficiency, scalability, and interpretability are also analyzed. Finally, future research directions are outlined, emphasizing hybrid learning approaches and integration with existing EDA workflows.

Keywords: Reinforcement Learning, Multi-Objective Optimization, Power Performance Area (PPA), VLSI Design, Electronic Design Automation, AI for Chip Design

Authors: Dev Prakash Sharma, Tribhuvan Pathak

Abstract: With the continuous scaling of semiconductor devices into sub-7nm and emerging 3nm nodes, the reliability and fault tolerance of integrated circuits have become critical design challenges. Advanced nodes exhibit increased susceptibility to process variations, soft errors, aging effects, and radiation-induced faults. Ensuring robust operation under these conditions requires novel fault-tolerant architectures, error detection and correction mechanisms, and reliability-aware design methodologies. This paper reviews key concepts in fault tolerance, analyzes challenges specific to advanced nodes, and discusses techniques including redundancy, error correction codes (ECC), adaptive body biasing, and monitoring circuits. Simulation and modeling approaches for reliability estimation are highlighted, along with emerging trends such as machine learning-assisted fault prediction. The paper aims to provide researchers and engineers with a comprehensive overview of strategies to improve fault tolerance and reliability in cutting-edge VLSI designs.

Keywords: Fault tolerance, reliability, advanced nodes, soft errors, process variation, aging effects, error correction codes, adaptive body bias, VLSI design.

Authors: Raghuveer Sriwastav, Kapil kant Tiwari

Abstract: The growing demand for high-performance, low-power, and compact electronic systems has driven the rapid integration of digital, analog, radio-frequency (RF), power, and sensor interfaces onto a single chip. Such systems, commonly referred to as mixed-signal and multi-domain chips, are fundamental to applications ranging from mobile devices and automotive electronics to biomedical instrumentation and industrial automation. However, the design of these chips poses significant challenges due to the coexistence of continuous-time analog behavior and discrete-time digital logic, coupled with strong interactions across voltage, power, thermal, and timing domains. Traditional electronic design automation (EDA) tools have been largely optimized for digital design, leaving analog and mixed-signal (AMS) design heavily reliant on manual expertise. This paper presents a comprehensive review of design automation techniques for mixed-signal, analog, and multi-domain chips. It discusses the evolution of AMS design flows, modeling and abstraction strategies, synthesis and optimization methods, verification and validation challenges, and emerging trends such as machine learning–assisted automation and multi-physics co-design. By highlighting both academic research and industrial practices, the paper aims to provide a consolidated perspective on the current state and future directions of AMS design automation.

Keywords: Mixed-signal design, analog automation, multi-domain chips, EDA tools, AMS verification, design optimization

Authors: Priya Rangan, Avshek Chaudhary, Vikash Sharma

Abstract: The rapid advancement in semiconductor technology has led to increasing demand for high-performance, energy-efficient, and cost-effective integrated circuits. Traditional monolithic system-on-chip (SoC) designs are facing scalability, yield, and thermal challenges as device dimensions continue to shrink. Chiplet-based and heterogeneous 3D system design approaches provide a promising alternative by integrating multiple smaller, function-specific dies into a single package. This paper reviews the fundamentals, architectures, design methodologies, and challenges associated with chiplet and heterogeneous 3D systems. We discuss the benefits of modular design, heterogeneous integration, advanced interconnect techniques, thermal management, and reliability considerations. Emerging trends, including co-packaged memory, advanced TSVs, silicon interposers, and AI-driven design tools, are highlighted. Tables and figures illustrate comparative performance metrics, integration strategies, and design workflows. The paper concludes with an outlook on future research directions, emphasizing the role of heterogeneous 3D systems in high-performance computing, AI accelerators, and next-generation consumer electronics.

Keywords: Chiplet, 3D integration, heterogeneous system design, TSV, silicon interposer, advanced packaging, modular SoC, thermal management

Authors: Manjusha D.Hedau, Naresh Pohane, K. N. Sawalakhe

Abstract: In the recent past, variable speed driving systems have found use in various small scale and large scale applications like automobile industries, domestic appliances etc. This lead to the development of Brushless DC motor (BLDCM). The use of BLDCM enhances various performance factors ranging from higher efficiency, higher torque in low-speed range, high power density, low maintenance and less noise than other motors. In this paper, implementation of hysteresis current controller with speed feedback loop is presented and it is observed that torque ripples are minimized. Simulation is carried out using MATLAB / SIMULINK. The results show that the performance of BLDCM is quite satisfactory for various loading conditions.

Keywords: Speed controller, Feedback loop, Brushless dc (BLDC) motor drive.

Authors: P. Nishanthi

Abstract: The aim of the project is to develop SPORT Verification IP using open verification methodology to verify SPORT module. Serial Communication Ports can operate at half the full clock rate at the processor, at a maximum data rate of n/2 Mbps, where n-equals the processor core clock frequency. Synchronous serial ports, or SPORTs, support a variety of serial data communications protocols and can provide a direct interconnection between processors in a multiprocessor system. Bidirectional functions provide flexibility for serial Communication. The motivation for the project is developing an OVM based verification environment which is able to perform the functional verification of the QSPI module and obtain a respectable coverage to avoid costly repines. Without it saving time and improving the verification effort by covering all the difficult corners of design and attaining maximum possible coverage will be difficult.

Keywords: Serial Port (SPORT), Open Verification Methodology (OVM), Intellectual Property (IP), System on Chip (SoC), Coverage Driven Verification (CDV).

Authors: Ravinder Chauhan, S. Meenal, Pradeep Kumar

Abstract: The continuous growth in semiconductor integration has resulted in system-on-chip (SoC) designs containing billions of logic gates. While this growth enables unprecedented computational capabilities, it also introduces significant verification challenges. Traditional simulation-based verification approaches struggle to provide adequate coverage and confidence at such scales. Formal verification, which relies on mathematically proving correctness properties, has emerged as a critical complement to simulation. However, classical formal techniques were originally designed for much smaller designs and do not directly scale to billion-gate systems. This paper presents a comprehensive review of formal verification methodologies and discusses how they are being adapted and scaled for ultra-large designs. Key techniques such as abstraction, compositional reasoning, property decomposition, hybrid formal-simulation flows, and hardware-software co-verification are examined in detail. Industrial case studies and tool flows are discussed to illustrate practical deployment challenges. The paper also highlights open research problems and future directions, including the use of machine learning and distributed computing to further improve scalability. The aim is to provide both academic researchers and practicing engineers with a consolidated understanding of state-of-the-art approaches for scaling formal verification to billion-gate designs.

Keywords: Formal verification, Billion-gate designs, SoC verification, Model checking, Abstraction, Scalability

Authors: Siwalika Pandey, Om Prakash Jha, Srivesh Singh, Umrawati Thakur

Abstract: The increasing reliance on embedded systems and Internet-of-Things (IoT) devices has made hardware security a paramount concern in Very Large Scale Integration (VLSI) design. Security-first VLSI design emphasizes integrating security mechanisms at the hardware level rather than relying solely on software protections. Two crucial components in this paradigm are Hardware Root of Trust (RoT) and Physically Unclonable Functions (PUFs). RoT provides a foundational anchor for secure operations, enabling secure boot, encryption key storage, and device authentication. PUFs exploit inherent manufacturing variability to generate unique, unclonable identifiers, offering lightweight and robust security solutions for authentication and anti-counterfeiting. This paper presents a comprehensive review of security-first VLSI design principles, focusing on RoT and PUF-based architectures, discussing design challenges, implementation strategies, and potential applications. The paper also outlines the current state-of-the-art, open research directions, and future trends in secure VLSI design.

Keywords: VLSI security, Hardware Root of Trust, Physically Unclonable Functions, secure IC design, hardware authentication, anti-tampering

Authors: Sanjay Dixit, Saroj Nair, Ashutosh Jain

Abstract: With the continuous scaling of semiconductor technologies and the rapid growth of system-on-chip (SoC) complexity, testing has become one of the most critical and cost-dominant phases in the integrated circuit (IC) design lifecycle. Traditional external testing approaches are increasingly challenged by limited observability, controllability, high test data volume, and rising test costs. Design for Testability (DFT) techniques and Built-In Self-Test (BIST) architectures have therefore emerged as essential components of modern VLSI design flows. This paper presents a comprehensive review of DFT and BIST enhancements, focusing on classical methods such as scan design and boundary scan, as well as recent advancements including test compression, low-power DFT, hierarchical test strategies, and intelligent BIST schemes. Memory BIST (MBIST), logic BIST (LBIST), and analog/mixed-signal BIST are discussed with emphasis on fault coverage, area overhead, and test time reduction. The paper also highlights challenges associated with nanoscale technologies, such as process variations and reliability concerns, and reviews emerging solutions to address them. The discussion aims to provide a balanced view of both academic research and industrial practices in DFT and BIST.

Keywords: Design for Testability, Built-In Self-Test, Scan Chains, Test Compression, MBIST, LBIST, SoC Testing

Authors: Sabita Thakur, P sreenivasan

Abstract: Functional verification has become the dominant cost and time factor in modern Very Large Scale Integration (VLSI) design cycles. With increasing design complexity, traditional verification methodologies struggle to provide sufficient coverage within reasonable schedules. Artificial Intelligence (AI) and Machine Learning (ML) techniques have recently emerged as promising solutions to accelerate verification tasks and automatically mine meaningful assertions from large simulation data. AI-accelerated verification improves test generation, bug detection, coverage closure, and regression optimization, while assertion mining enables automatic extraction of temporal properties from design behavior. This paper presents a comprehensive review of AI-driven verification methodologies and assertion mining techniques, highlighting their principles, workflows, benefits, and limitations. We discuss supervised, unsupervised, and reinforcement learning approaches applied to simulation-based and formal verification environments. A detailed comparison between conventional verification and AI-accelerated approaches is also provided. Challenges such as scalability, explainability, data quality, and industrial adoption are analyzed. Finally, future research directions toward trustworthy, hybrid AI-assisted verification frameworks are outlined.

Keywords: AI in VLSI, Functional Verification, Assertion Mining, Machine Learning, Formal Verification, Coverage Optimization

Authors: Sandeep Verma, Anil Bajaj

Abstract: In this paper, the increasing convergence of communication systems with computing, and how this trend is going to continue, is highlighted. According to Moore’s law, the number of transistors used in a given area doubles every 18 months. This means that within 18 months, you can expect communication technology to move to the next level, and that’s why we are experiencing such a fast-paced information revolution nowadays. The balance between telecom and power distribution is essential to enable this distribution. This paper will highlight the convergence of computing and data communications as well as the essential power management architecture that keeps it going.

Keywords: VLSI Communication, Telecom and Computing, VLSI based Convergence

Authors: Dharmendra Ray, Balram Pathak, Surabhi Chauhan, Baban Tiwari

Abstract: As semiconductor technology approaches the sub-nanometer (sub-nm) regime, ensuring reliable operation of integrated circuits (ICs) becomes increasingly challenging. Both timing and power integrity critically influence performance, yield, and reliability in advanced technology nodes. Sub-nm designs face heightened variability, increased leakage currents, and significant signal and power noise, making traditional analysis methods insufficient. This paper reviews state-of-the-art techniques in timing and power integrity analysis, highlighting challenges specific to sub-nm designs, methodologies for mitigation, and emerging trends in modeling, simulation, and validation. Furthermore, the paper discusses multi-objective approaches that balance power, performance, and area (PPA) while maintaining signal and power integrity. Finally, case studies, tools, and methodologies are examined to guide designers in practical sub-nm IC design workflows.

Keywords: Sub-nm VLSI, Timing Analysis, Power Integrity, Signal Integrity, EM/IR Analysis, Variation-Aware Design, Advanced Nodes

Authors: Anuj Kumar, Sudhir Mishra, Shalini Shahay

Abstract : Wireless telephones of this day and age are more than merely an instrument of voice transfer. They come with loads of features and use up their battery quickly. In this paper, we present the subsystem design requirements for optimizing use of power in these phones. Smartphones, as many wireless telephones are popularly called, come integrated with global position system (GPS), music player, digital camera, and other features. Without power optimization, it would be difficult for a smartphone to retain power for running the different applications installed in it. Integration of different technologies in a handheld phone requires power optimization for each of its subsystem.

Keywords: Wireless Telephone Design, Power Optimization In Smartphones, Technology Integration In Smartphones

Authors: B.Vidhya

Abstract: Cognitive radio is a wireless communication technology which adds intelligence to the existing wireless communication scenario. This concept arises due to the heavy occupancy of frequency spectrum below 3 GHz which is caused by the ever growing demand for wireless services by the customers. This problem has placed a heavy burden to the resource allocation policy maker to accommodate between the demand and the available spectrum resources. In this paper, we address the problem of resource allocation in the context of cognitive radio networks (CRN).With the deployment of K antennas at the cognitive base station(CBS), an efficient transmit beamforming technique is proposed to maximize the Signal to noise ratio. We also used the smart antenna beamforming technique to enhance the error rate performance of the system. We simulated the result using MATLAB 7.5 and finally we analyzed the results for two cases, one when adaptive beamforming is used in the proposed system and second when adaptive beamforming is not used in the proposed system.

Keywords: Cognitive radio, beamforming, SINR, smart antenna, wireless communication