Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors:-Mr. R. Venkatesh, Dr. Soumya Banerjee

Abstract:-Front-end VLSI design plays a critical role in the successful development of modern integrated circuits by ensuring functional correctness and design reliability before fabrication. Register Transfer Level (RTL) modeling and verification constitute the foundation of the front-end design flow, where hardware description languages and verification methodologies are extensively employed. A wide range of commercial and open-source front-end VLSI design tools are available, each offering distinct features, strengths, and limitations. This paper presents a comparative study of widely used front-end VLSI design tools for RTL modeling and verification. The study evaluates these tools based on language support, simulation performance, verification capabilities, ease of use, scalability, and suitability for academic and industrial applications. Through qualitative and quantitative analysis, this paper highlights the effectiveness of different tools in addressing verification challenges associated with complex system-on-chip designs. The results provide valuable insights for researchers, educators, and design engineers in selecting appropriate front-end tools for efficient VLSI design and verification.

Keywords: Front-End VLSI Design, RTL Modeling, Functional Verification, HDL Simulation, EDA Tools

Authors: Dr. M. Srinivasan, Ms. Ananya Ghosh

Abstract: Clock Tree Synthesis (CTS) is a critical stage in the VLSI physical design flow, directly influencing the performance, power consumption, and reliability of synchronous digital systems. As technology nodes scale into deep nanometer regimes, clock distribution has become increasingly challenging due to higher clock frequencies, stringent skew requirements, increased process variations, and power constraints. Modern VLSI physical design tools incorporate advanced CTS optimization techniques to balance clock skew, latency, power, and signal integrity. This paper presents a comprehensive study of clock tree synthesis optimization techniques employed in contemporary VLSI physical design tools. The paper discusses CTS fundamentals, clocking challenges at advanced nodes, optimization strategies, and integration of CTS with timing and power closure. Tables and conceptual figures are used to illustrate clock structures, optimization trade-offs, and tool capabilities. The paper concludes by outlining future trends in clock tree optimization for next-generation VLSI designs.

Keywords: Clock Tree Synthesis, VLSI Physical Design, Clock Skew, Clock Power, CTS Optimization, EDA Tools

Authors:-Dr. Aniket S. Kulkarni, Dr. Rina Sen

Abstract: Floorplanning is a critical step in VLSI physical design, determining the placement of functional blocks and interconnect routing to optimize area, performance, and power. Traditional manual floorplanning is time-consuming and prone to suboptimal solutions. The integration of optimization algorithms and CAD tools has enabled automated floorplanning, reducing design iteration time and improving quality-of-results (QoR). This paper reviews modern approaches for automated VLSI floorplanning, including simulated annealing, genetic algorithms, particle swarm optimization, and analytical methods, evaluates their integration with CAD tools, and explores emerging research trends in multi-objective and machine learning-assisted floorplanning.

Keywords: VLSI floorplanning, CAD tools, Optimization algorithms, Automated design, Physical design, QoR.

Authors: Dr. K. Srinivasa Rao, Ms. Ananya Chatterjee

Abstract: Very Large Scale Integration (VLSI) design has entered an era of extreme complexity driven by aggressive technology scaling, heterogeneous integration, and demanding power–performance–area (PPA) requirements. Traditional electronic design automation (EDA) tools rely heavily on deterministic algorithms and rule-based heuristics, which increasingly struggle to manage the exponential growth of design constraints and solution spaces. Artificial Intelligence (AI), particularly machine learning (ML), has emerged as a promising paradigm to augment and automate various stages of the VLSI design flow. This paper presents a comprehensive study of AI-assisted VLSI design automation using machine learning techniques. It explores the application of supervised, unsupervised, and reinforcement learning across front-end and back-end design phases including logic synthesis, placement, routing, timing closure, power optimization, and verification. The paper discusses architectural integration of ML models within existing EDA flows, analyzes benefits and limitations, and presents comparative evaluations through tabulated results and conceptual figures. The study concludes that AI-driven automation significantly improves design productivity, reduces turnaround time, and enhances PPA optimization, while also highlighting open research challenges such as data quality, model generalization, and explainability.

Keywords: VLSI Design Automation, Machine Learning, EDA Tools, AI-Driven Optimization, Physical Design, Timing Closure.

Authors: Dr. Anil R. Deshmukh, Dr. Supriya Chatterjee

Abstract: The design of analog and mixed-signal (AMS) VLSI circuits presents unique challenges that differ significantly from digital-only VLSI systems. The increasing complexity of System-on-Chip (SoC) integrations, stringent performance requirements, and variability in deep submicron processes necessitate robust design automation tools. This paper reviews the state-of-the-art analog and mixed-signal VLSI design tools, highlights challenges such as device non-linearity, process variation, and simulation runtime, and discusses emerging trends including machine learning-assisted optimization, multi-level abstraction, and co-simulation methodologies. A comparative analysis of tools and methodologies is provided, along with a discussion on integration of analog verification, layout, and parasitic extraction into a seamless design flow.

Keywords: Analog VLSI, Mixed-Signal Design, CAD Tools, Process Variation, AMS Simulation, Design Automation.

Authors: Diksha R. Bhil 

Abstract: Electric fences can be used to protect farmhouses, farmlands, forest bungalows, etc from animals. In a way, these simulate the job of a cowboy or forest guard. Already popular in countries where manpower is expensive, electric fences are slowly becoming popular in India as well. These control the animals by giving them a short, sharp but safe shock that teaches them to stay away from the fence. Thus electric fences are economical and practical solutions to maximize field production through controlled grazing. Electric fencing is safe, as its output is discrete (not continuous). There is certain time duration between two pulses that prevents prolonged shocking to animals or people. In addition, the short ‘on’-time (normally 1/5000th of a second) prevents heat build-up.

Keywords: GSM, PIR Sensor, LCD display.

Authors: Neha Waitage, Shrushti Panpaliya, Nita Suryavanshi, Ankita Veruklkar

Abstract:  In recent years with the improvement of net generation, the internet of things (IoT) has all started to use to every domain. The paper introduces the concept a way to observe iot to the accelerator control gadget and take the present manipulate gadget of the BEPCII power substances for example for IoT utility. it no longer handiest introduce the fame of the manipulate gadget of the BEPCII power components, but also gift an answer the way to practice IoT to the present manipulate gadget. the cause is to make the control system greater wise and routinely become aware of what and in which the hassle is while the alarm of the control machine of the energy substances occurs. which means that IoT can assist to automatically pick out which chassis and which module inserted within the chassis and the relationship cables. it is super handy for the maintainer to apply a cellular smart phone to diagnose faults and create the electronic renovation record.

Keywords: Internet of Things, Electronic renovation record, RFID, BEPCII

Authors: Mr. R Rajaguru, T Abdus Shakur, G Durga, K Naveen Kumar, M Samradul Afra,
L Sivasankari

Abstract: This project deals with integrated Automatic control systems for Wiper speed based on rainfall density and Head light Modes .The drivers of most vehicles use high beam while driving at night. This causes a discomfort to the person travelling from opposite direction .The driver experience a sudden glare for short period of time and causes temporary blindness to the person resulting in road accidents during night time .To avoid such incidents, the proposed model automatically switches high beam into low beam thus reducing glare effect by sensing the approaching vehicle using ldr sensor. In order to avoid the problem, the proposed model implements automatic wiper system which detects the rain and its density by using rain sensor and according to the rain density, the wiper speed is automatically controlled as programmed. Gas sensor is used to detect presence of alcohol and if it found entire system will be automatically disabled.

Keywords: Atmega8, Gas sensor, Ldr sensor, Rainfall sensor, Wiper Motor

Authors: S.Shanthini, M. Joe Marshell

Abstract: The main aim of this project is to monitor the leakage of gas which used in households and restaurants to avoid fire accidents providing safety feature for the environment where security has been an important issue. The most common problem experienced in our day- to- day lives that is regarding GAS leakage system. When it comes it to safety of the surrounding  as well as gas container we have an MQ-5(gas sensor), which will detect the gases by  propane, butane, carbon monoxide ,smoke ,alcohol etc. The system detects the leakage of LPG using gas sensor and When the system detects the LPG concentration in the air exceeds the certain level then it immediately takes action by automatically.  Thus here we are using the gas sensor which placed in the leak points, which senses the concentration value of  gases such as propane ,butane ,smoke ,alcohol , carbon mono-oxide etc  and when the concentration value exceeds the normal value the leakage of gas is detected , and alert system used by buzzer and  the automatically open the windows prevent fire accidents. The gas sensor has been used which has high sensitivity to gases like propane and butane. When the concentration of LPG in air exceeds a certain level, the sensor senses the gas leakage and the output of the sensor goes LOW. The detection is done by the gas sensor, through the microcontroller the LED and buzzer are turned ON simultaneously. Using relay DC motor is automatically open the windows.

Keywords: gas sensor (MQ-5) , Microcontroller , buzzer , LPG, Dc Motor , Relay.

Authors: Dr. M. Suresh Kumar, Ms. Payel Mukherjee

Abstract: Timing analysis and timing closure have become increasingly complex and critical in nanometer VLSI technologies due to aggressive device scaling, higher operating frequencies, and growing design variability. As integrated circuits move into deep submicron and nanometer regimes, traditional static timing analysis techniques face challenges arising from process variations, interconnect dominance, power integrity issues, and multi-mode multi-corner constraints. Achieving timing closure now requires coordinated optimization across logic synthesis, physical design, and sign-off analysis using advanced EDA tool capabilities. This paper presents a comprehensive study of timing analysis methodologies and the major timing closure challenges encountered in nanometer VLSI technologies. The paper examines the impact of scaling on timing behavior, discusses advanced static timing analysis models, and reviews tool-based optimization techniques for setup and hold closure. Comparative tables and conceptual figures are used to illustrate timing violations and optimization outcomes. The paper concludes by identifying open challenges and future research directions in timing-aware VLSI design automation.

Keywords: Timing Analysis, Timing Closure, Nanometer VLSI, Static Timing Analysis, Process Variations, Physical Design Optimization

Authors: Dr. S. Venkatesh, Ms. Ritu Chatterjee

Abstract: Technology scaling has been the primary driving force behind the exponential growth of integrated circuit performance and functionality over the past several decades. As transistor dimensions shrink into deep nanometer and sub-nanometer regimes, VLSI design tools and workflows have undergone substantial transformation to cope with new physical, electrical, and manufacturing challenges. Traditional design assumptions related to timing, power, variability, and reliability are no longer valid at advanced technology nodes. This paper presents a comprehensive study on the impact of technology scaling on VLSI design tools and workflows. The discussion covers the evolution of scaling trends, emerging challenges such as process variations and interconnect dominance, and the corresponding adaptations in Electronic Design Automation (EDA) tools. Tables and conceptual figures are used to illustrate workflow changes and tool enhancements. The paper concludes by highlighting future directions in scalable VLSI design methodologies.

Keywords: Technology Scaling, VLSI Design Tools, EDA Workflows, Nanometer Technologies, Design Automation

Authors: Dr. R. Karthikeyan, Ms. S. Banerjee

Abstract: The increasing complexity of VLSI systems, driven by advanced applications such as artificial intelligence, high-speed communication, and embedded computing, has significantly increased the demand for rapid design cycles and higher productivity. Traditional Register Transfer Level (RTL) design methodologies, although precise, are time-consuming and require extensive manual effort. High-Level Synthesis (HLS) has emerged as a transformative approach that bridges the gap between high-level algorithmic descriptions and hardware implementations. HLS tools automatically translate behavioral descriptions written in high-level languages into optimized RTL code, enabling faster design space exploration and improved productivity. This paper presents a comprehensive study of High-Level Synthesis tools and their role in accelerating VLSI design productivity. The paper discusses HLS fundamentals, tool workflows, optimization techniques, advantages over conventional RTL design, and challenges associated with adoption. Comparative tables and conceptual figures are included to analyze productivity gains and performance trade-offs. The study concludes by highlighting emerging trends and future research directions in HLS-based VLSI design.

Keywords: High-Level Synthesis, VLSI Design Automation, Hardware Acceleration, Design Productivity, EDA Tools

Authors: Dr. A. Natarajan, Ms. Ishita Paul

Abstract: Physical verification is a critical sign-off stage in the VLSI design flow, ensuring that a layout is both manufacturable and functionally equivalent to its intended design. Among physical verification tasks, Design Rule Checking (DRC) and Layout Versus Schematic (LVS) verification play a central role in preventing fabrication failures and functional mismatches. With the transition to nanometer and sub-nanometer technologies, the complexity of design rules and verification requirements has increased dramatically. Modern VLSI tools must handle complex geometric constraints, multi-patterning rules, and hierarchical designs while maintaining reasonable runtimes and accuracy. This paper presents a comprehensive study of DRC and LVS verification using modern VLSI tools. The paper discusses the fundamentals of DRC and LVS, evolving challenges at advanced technology nodes, and the role of contemporary EDA tools in automating physical verification. Comparative tables and conceptual figures are included to illustrate verification flows, error types, and optimization outcomes. The study concludes by highlighting current challenges and future trends in physical verification automation.

Keywords: Physical Verification, Design Rule Checking, Layout Versus Schematic, VLSI Tools, Nanometer Technologies, Sign-Off Verification

Authors: K Uday Kumar Reddy, K Sainadh Singh, Dr. N Bhoopal

Abstract: This paper   presents   a   new   way   to   design   PID controller for both integer order and fractional order with a time delay for a typical interacting cylindrical tank system using MATLAB FOMCON toolbox.  Here,  our  work  aims  to  study  the performance characteristics of integer order and fractional order PID  controller  on  the  current  integer  order  plant  obtaining minimum  objective  function  by Nelder –Mead optimization technique  with  different  performance  metrics  ISE,  ITSE  and IAE.  Next  our  work  shows  to  make comparison  between integer order  PID  controller  based  on  AMIGO  model  performance and fractional  order  PID  controller  on  time  domain  characteristics. The proposed  method  aims  finally  to  analyse  overall  desired performance  on  fractional  order  PID  controller  by  adding  two extra  degrees  of  freedom  over  the  integer  order  PID  controller with different performance criteria.

Keywords: Coupled tank,    AMIGOIO controller, FO controller, Nelder-Mead optimization, FOMCON toolbox

Authors:- Bijendra Singh, Sambhunarayan Pandey, Diwanky Dubey

Abstract:-The rapid evolution of digital system design has necessitated innovative approaches for accelerating hardware development cycles. Register Transfer Level (RTL) and Hardware Description Language (HDL) generation are critical phases in digital circuit design, traditionally requiring expert knowledge and substantial manual effort. Recently, Large Language Models (LLMs) have demonstrated unprecedented capabilities in natural language understanding and code generation. Their application to RTL/HDL generation offers promising avenues for automating design, reducing development time, and minimizing errors. This paper provides a comprehensive review of the state-of-the-art in LLM-assisted RTL/HDL generation, exploring their architectures, training methodologies, challenges, and potential integration into Electronic Design Automation (EDA) workflows. Additionally, we analyze the performance of LLM-generated designs compared to traditional human-engineered RTL code and discuss future research directions.

Keywords: Large Language Models, RTL Generation, HDL, Digital Design Automation, AI-Assisted Hardware Design, Electronic Design Automation, Hardware Description Language.

Authors:- K Uday Kumar Reddy, K Sainadh Singh, Dr. N Bhoopal

Abstract:-This paper presents a new way to design PID controller for both integer order and fractional order with a time delay for a typical interacting cylindrical tank system using MATLAB FOMCON toolbox. Here, our work aims to study the performance characteristics of integer order and fractional order PID controller on the current integer order plant obtaining minimum objective function by Nelder –Mead optimization technique with different performance metrics ISE, ITSE and IAE. Next our work shows to make comparison between integer order PID controller based on AMIGO model performance and fractional order PID controller on time domain characteristics. The proposed method aims finally to analyse overall desired performance on fractional order PID controller by adding two extra degrees of freedom over the integer order PID controller with different performance criteria.

Keywords: Coupled tank,  AMIGOIO controller, FO controller, Nelder-Mead optimization, FOMCON toolbox

Authors:-K Uday Kumar Reddy, K Sainadh Singh, Dr. N Bhoopal

Abstract:- In recent years, the development in the deregulated electricity market structure increases the number of market participants thereby, makes the market more competitive. Therefore, it is important for the system operator to determine fast and accurate static available transfer capability (S-ATC) of the system to provide secure electricity power wheeling. This paper proposes the fast assessment of S-ATC in the deregulated environment by eliminating the Contingency pre-screening process. Application of Real coded genetic algorithm (RGA) is used as a tool in determining S-ATC without finding severe contingencies. The effectiveness of the proposed method of ATC assessment is analysed by carry out different bilateral/multilateral wheeling transactions on Sample six bus system and it is accuracy compared with the Conventional Repeated Power flow Method.

Keywords: Component; Formatting; Style; Styling; Insert

Authors: Nisha O. S, Dr. K. Siva Sankar

Abstract: Today’s submicron VLSI technology has been emerged as integration of many VLSI ICs into a single Si Chip called System-on-Chip (SoC). The SoC architecture normally contains multiple processors along with either separate or centralized memory blocks as its core elements as well as many noncore elements. Embedded RAMs are those whose address, data, and read/write controls cannot be directly controlled or observed through the chip’s 1/0 pins. Testing these memories, which are incorporated on a large percentage of VLSI devices are harder just because of the lack of controllability of its inputs and observe ability of its outputs. Testing such RAMs is the main objective of this paper. It is challenging to test embedded RAMs, and hence we will discuss techniques - design for testability (DFT) and built-in self-test (BIST), which help in improving the testability of these RAMs.

Keywords: Built-In Self-Test (BIST), March Algorithm, Switching Factor

Authors: Prakash Kerur, Dr. R.L. Chakrasali

Abstract: Solar energy is inexhaustible, available abundant in nature and free from pollution. The solar photovoltaic (PV) systems are a perfect solution for power requirement urban residential areas since the system is noiseless. The main problem with solar energy is its intermittency. However, sometimes during clear days the solar panels generate surplus power beyond the needs. At these times, the surplus power is exported into the main utility grid. With increase of renewable energy sources causes various problems of grid integration to export the surplus power. The concept of digital grid (DG) and bi-directional smart meters are the solution for these problems. The digital grid” where a wide-area synchronized power system is sub divided into smaller or medium sized power systems. Subdivided grids called “digital grid cells” are connected together asynchronously via “digital grid routers”. The DGR is a multi-terminal AC/DC/AC power conversion device. In order to construct a DG, bi-directional power flow and asynchronous interconnection of many distributed solar roof tops. If the solar PV panel produces surplus power, then it has to be supplied to the grid and the exported surplus power must be accounted. The smart energy meter has to account for imported power from the grid to consumer system and the exported power from the consumer system to grid. In this paper Digital grid router (DGR) and smart meter combination are discussed.

Keywords: Digital Grid Router (DGR), Smart meter, Bi-directional power flow, Renewable Energy Sources

Authors: Anand Shekhar, Vivek Sinha

Abstract: Electronic Design Automation (EDA) has been a cornerstone of modern integrated circuit (IC) and system-on-chip (SoC) design. Traditional EDA workflows rely heavily on heuristic and rule-based methodologies to optimize design parameters such as timing, area, and power. However, with the exponential increase in design complexity, conventional techniques often struggle to deliver efficient solutions within acceptable timelines. Artificial Intelligence (AI), particularly Machine Learning (ML) and Deep Learning (DL), has recently emerged as a transformative tool for enhancing EDA workflows. AI-driven methods facilitate intelligent automation in tasks like placement, routing, timing closure, verification, and predictive design analytics. This paper provides a comprehensive review of AI-enhanced EDA workflows, examining the integration of ML techniques, algorithmic improvements, and real-world applications. It also highlights the benefits, challenges, and future research directions in this emerging field.

Keywords: Electronic Design Automation, Artificial Intelligence, Machine Learning, Deep Learning, IC Design, Predictive Analytics, Placement and Routing

Authors: Ankur Singh, Amna Chandra

Abstract: Three-dimensional integrated circuits (3D ICs) are revolutionizing semiconductor design by offering significant advantages in device density, performance, and power efficiency. The advent of Through-Silicon Vias (TSVs) and monolithic stacking has enabled vertical integration of circuits, reducing interconnect lengths and improving signal integrity. This paper reviews the fundamentals of 3D ICs, focusing on TSV-based integration and monolithic 3D stacking, highlighting the design challenges, manufacturing techniques, thermal management strategies, and emerging applications. A comparative analysis of TSV and monolithic stacking approaches is provided, alongside a discussion of future research trends. The insights presented aim to guide researchers and engineers in the development of next-generation high-performance and energy-efficient integrated circuits.

Keywords: 3D IC, Through-Silicon Via (TSV), Monolithic Stacking, Vertical Integration, Thermal Management, High-Density Integration.

Authors: S. Thirumala Devi, V. Vijay Kumar Raju

Abstract: Device feature-size reduction is becoming dominant in the semiconductor industry, its impact on product reliability, yield, and therefore cost is dramatically increasing. Embedded microprocessors and other highperformance on-chip modules incorporate Static Random Access Memory (SRAM) or cache components that play significant roles in overall chip functionality and reliability. The static power in on-chip SRAM can dominate the total system power during low switching activity. Thus, in order to reduce power consumption, SRAM technologies with significantly lower leakage currents are needed. Numerous prominent publications have appeared over the recent years targeted at SRAM power reduction in an effort to reduce the overall power consumption of the chip. The work presented in this paper, ultra-low-power embedded SRAM bit cell is investigated by providing positive feedback using Schmitt Trigger concept increasing the stability, and reduce the leakage current, due to this power consumption also reduced. The conventional 6T SRAM, 7T, 9T, 10T, Schmitt Trigger based SRAM bit cell are compared in terms of power dissipation.

Keywords: - Low-Power SRAM, process variation, Schmitt Trigger (ST).

Authors: B Kishore, P Chandra Babu, Dr. B. Venkata Prasanth

Abstract: An active power filter implemented with a four-leg voltage-source inverter using a predictive control scheme is presented. The use of a four-leg voltage-source inverter allows the compensation of current harmonic components, as well as unbalanced current generated by single-phase nonlinear loads. A detailed yet simple mathematical model of the active power filter, including the effect of the equivalent power system impedance, is derived and used to design the predictive control algorithm. The compensation performance of the proposed active power filter and the associated control scheme under steady state and transient operating conditions is demonstrated through simulations and experimental results.

Keywords: Active power filter, current control, four-leg converters, predictive control, PI, FUZZY

Authors:-Hitlendra Pratap Singh , Dr. G.S. Virdi

Abstract:-An analytical delay model is proposed for RLC modeled high speed on-chip VLSI interconnects based on a second order approximate transfer function in DSM technology environment. The proposed analytical delay model is almost independent of the ratio of V_o/V_i (output voltage to input voltage) and the driver resistance (R_D) has an impact on the delay correspondingly speed and reliability of the circuit gets affected. It is observed that real pole model provides better accuracy and is much faster than the complex pole model. An analytical delay model for RLC interconnect line with complex and real poles based on a second order approximation that considers the effect of inductance and incorporates ground capacitance. The impacts of driver/source resistance and output load capacitance have also been taken into account. For a wide range of driver, load, and interconnect line parameters the delay of the circuit model is calculated. It is observed that the average error rate of our developed models (both real and complex pole models) is within 10.49% and 10.14% with HSPICE simulation.

Keywords-Delay model, Transfer function, RLC Interconnect, complex poles, real poles

Authors: Vimal Mehta, Subham Singh, Kunal Deshmukh

Abstract: Hardware-Software Co-Design (HSCD) has emerged as a pivotal methodology in the development of high-performance and energy-efficient System-on-Chips (SoCs). With the increasing complexity of modern SoCs driven by multi-core processors, heterogeneous architectures, and AI workloads, traditional sequential design approaches often fall short in meeting performance, power, and area (PPA) constraints. HSCD allows concurrent optimization of hardware and software components, enabling early exploration of design trade-offs and accelerating time-to-market. This paper reviews the state-of-the-art in HSCD techniques, explores modeling and simulation approaches, discusses design automation tools, and presents real-world case studies demonstrating efficiency gains in SoCs. The challenges and future trends, including AI-assisted co-design and reconfigurable platforms, are also analyzed.

Keywords: Hardware-Software Co-Design, System-on-Chip, Embedded Systems, Design Automation, Energy Efficiency, Heterogeneous Architectures, Performance Optimization.