Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors:Atul Ramdas Chandanvadan, Kunal Deshmukh

Abstract:Very large-scale integration (VLSI) is the process of integrating a large number of electronic components onto a single semiconductor chip. This has enabled the development of increasingly complex and powerful electronic devices, such as microprocessors, memory chips, and digital cameras. VLSI design is a challenging task, but it is essential for the continued development of modern technology. The power of VLSI design in modern technology begins by providing an overview of VLSI technology, including its history, advantages, and challenges. The paper then discusses the importance of power in VLSI design, and presents some of the techniques that are used to reduce power consumption. Finally, the paper discusses the future trends in VLSI design.

Keywords: -VLSI design, Power consumption, Low-power design, Very largescale integration, Electronic devices, Microprocessors, Memory chips, Digital cameras

Authors:Dr. S. B. Kemdarne, Viren Garg

Abstract:Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI design tools and technology have evolved significantly over the years, leading to a number of important advances in the field. This paper provides a comprehensive overview of the evolution of VLSI design tools and technology, and discusses the impact of these advances on the design of VLSI circuits. The paper begins by discussing the early days of VLSI design, when tools were limited and the design process was very manual. It then describes the development of new tools and techniques that have made VLSI design more efficient and less error-prone. These include the use of computer-aided design (CAD) tools, the development of new design methodologies, and the use of new materials and fabrication processes. The paper then discusses the impact of VLSI design tools and technology on the design of VLSI circuits. These advances have led to a number of important benefits, including:

• Smaller and more complex circuits
• Faster and more efficient circuits
• Lower power consumption
• Increased reliability
• Reduced cost

Keywords:-VLSI, design tools, technology, evolution, impact, CAD, design methodology, materials, fabrication process

Authors:Raghuvash Mehra

Abstract:Very Large Scale Integration (VLSI) is the process of integrating millions or billions of transistors onto a single chip. It has revolutionized the electronics industry, enabling the development of powerful computers, smartphones, and other devices. However, the traditional approach to VLSI design is reaching its limits. As transistors continue to shrink, the challenges of heat dissipation, power consumption, and signal integrity become increasingly difficult to overcome. This paper surveys the latest innovations in VLSI design for advanced electronics. We discuss new approaches to transistor scaling, power management, and signal integrity. We also explore emerging technologies such as 3D ICs, neuromorphic computing, and quantum computing.

Keywords:-VLSI design, Moore's Law, Transistor scaling, Power management, Signal integrity, 3D ICs, Neuromorphic computing, Quantum computing, Emerging technologies, Electronics, Technology, Innovation

Authors:Sushma P S , Arundathi Manoj

Abstract:This study uses a field programmable gate array (FPGA) to provide serial data transfer utilizing an I2C (Inter-Integrated Circuit) master bus controller. MAXIM DS1307, which serves as a slave, was interfaced with the I2C master bus controller. Model-Sim was used to simulate this module after it was created in Verilog HDL. Xilinx ISE Design Suite was used to synthesize the design. I2C master starts the data transfer, and then the slave answers in the proper sequence. It can connect low-speed peripherals such motherboards, embedded systems, mobile phones, set-top boxes, DVD players, PDAs, and other electronic devices.

Keywords:- I2C (Inter-Integrated Circuit), Verilog HDL, Xilinx ISE Design Suite, Model-Sim.

Authors:Rudraksh Negi

Abstract: In recent years, there has been a growing demand for teaching VLSI design in a project-based approach. This paper presents a teaching method that is ideal for VLSI design courses with small budgets. The proposed method emphasizes hands-on learning and encourages students to learn by doing. The course is designed to provide students with a solid foundation in VLSI design principles and techniques, and to help them develop the skills and experience needed to work in the field of VLSI design. The paper also describes the various tools and technologies that are used in the course, along with a detailed description of one of the projects.

Keywords: VLSI design, project-based learning, hands-on learning, small budgets, teaching method, tools.

Authors: Atul Negi, Praveen Kumar, Alok Pandit

Abstract: The field of Artificial Intelligence (AI) has made tremendous progress in recent years, with many new applications emerging. The development of Very Large Scale Integration (VLSI) technology has also been a crucial factor in advancing AI, as it has enabled the creation of faster and more efficient computer hardware. In this review paper, we explore the application of VLSI in Artificial Intelligence, including its history, current state, and future prospects. We also examine the various applications of AI and VLSI, including deep learning, neural networks, and image recognition. We conclude that the integration of AI and VLSI has the potential to revolutionize various industries, from healthcare to finance.

Keywords: Artificial Intelligence, VLSI, Deep Learning, Neural Networks, Image Recognition.

Authors: Shivay Malohtra, Ramesh Kumar, Aakash Gehlot

Abstract:Wireless sensor networks have seen tremendous growth and advancement over the years, owing to their ability to sense, process and transmit data wirelessly. In this paper, we present a mixed-signal based VLSI technology for wireless sensor networks. Our proposed solution is based on Programmable System-on-Chip (PSoC) architecture, which integrates both digital and analog circuits on a single chip. We present the PSoC design flow, along with the implementation of a wireless sensor node based on PSoC. Our sensor node includes a humidity sensor, RF module, and software for data processing. We present experimental results and discussions, along with the implementation of a wireless sensor network. Our proposed solution offers a low-cost, low-power and flexible platform for wireless sensor networks.

Keywords: Wireless Sensor Networks, VLSI Technology, Mixed-Signal, PSoC, Humidity Sensor, RF Module

Authors: Abhinav

Abstract: Very large scale integration (VLSI) testing is an essential process for ensuring the proper functionality of integrated circuits (ICs). The scan design technique is a widely used method for testing ICs. This paper provides a comprehensive study of popular VLSI test scan architectures, including their working principles, advantages, and disadvantages. The study includes the basic scan architecture, modified scan architecture, and the recently introduced Hybrid Test Scan Architecture (HTSA). The paper also discusses various issues and challenges associated with scan testing, such as power consumption and test data volume. This paper will provide valuable insights into the different scan architectures used in VLSI testing and their limitations, which can be helpful for researchers and engineers involved in VLSI testing.

Keywords:VLSI, testing, scan design, scan architecture, basic scan, modified scan, HTSA, power consumption, test data volume.

Authors: Vikash Kumar, Rishik Jaiswal, Prakriti Singh

Abstract: In recent years, the demand for smart parking systems has increased due to the shortage of parking spaces in urban areas. The fuzzy logic-based automatic car parking system is an efficient solution to address this problem. This paper presents a comprehensive review of the design of low-power VLSI architecture and ASIC implementation of a fuzzy logic-based automatic car parking system. The proposed system uses a fuzzy logic controller to control the movement of a car within a parking lot. The system is designed to minimize the power consumption while ensuring the accuracy and reliability of the parking process. The design of the system involves the selection of suitable sensors, the development of a fuzzy logic controller, and the implementation of the system on an ASIC. The performance of the system is evaluated based on various parameters such as power consumption, accuracy, and reliability. The results show that the proposed system is efficient and effective in controlling the movement of a car in a parking lot.

Keywords: Fuzzy logic, Automatic car parking system, Low power VLSI architecture, ASIC implementation.

Authors:-Archit Halder, Saurabh Gajanan Bhokare,Basanta Bhowmik

Abstract:-The current study proved the utilisation of several error detection and repair technologies that provide trustworthy data transmission quality. The current state of technological growth necessitates efficient and dependable data transmission technologies. During data transmission (from source to destination), there is a significant risk of erroneous data at the destination (due to noise inclusion). Keeping this in mind, the current research examined one strategy for expounding the digital design conversion of a Viterbi decoder. The decoder employs the Viterbi method and performs digital design conversion of a (2, 1, 4) Convolution Encoder with a constraint length of L=5 and code rate of ½. The design was validated using the Verilog hardware description language (HDL). The XILINX ISE 14.5 simulator was then used for synthesis and simulation.

Keywords:-Viterbi Decoder, (2,1,4) Convolutional Encoder, Viterbi algorithm, Trellis structure.

Authors:-Tejinder Singh_, Nitish Sharma

Abstract:-This article begins with general information on the VLSI and then moves on to the history and advancement of the VLSI. MOORE'S LAW is now understood, and the structure of VLSI via HIERARCHY-STRUCTURE clarifies the planning of VLSI circuits. In this work, a part of the general discussion on current leakage reduction in processors is evaluated, in which the reduction of current leakage by using switches is integrated, and we can moreover lessen the current leakage in the circuit by employing “slumber transistor". Sleep transistors are transistors that totally switch off while the circuit is not in use. This is a highly good strategy. Following that, some of the issues with incorporating sleep transistors are covered, which is critical when constructing any circuit.

Keywords:-Current Losses, Circuits, RAM, ROM, Transistors, Moore’s Law.

Authors:-Gourav Kumar, Nikhil Saxsena, Dr. Pankaj Rastogi

Abstract:-Artificial Intelligence (AI) and Machine Learning (ML) advancements have encouraged complicated designs to be incorporated in Very Large-Scale Integration (VLSI) Design. Designers are focusing on high speed and low power solutions to meet the needs of the technology. The Digital Signal Processor is the building block in many AI applications; optimising it may solve challenges connected to computing data signals at a quicker rate while spending less power utilising Vedic mathematics. This study provides a full assessment of contemporary applications of Vedic Mathematics in the realm of VLSI to provide unique design, efficient architecture for Squarer, Multiplier, Arithmetic unit, Cubic, and division circuits, as well as their critical performance requirements. The employment of Vedic Sutras in the formulation of algorithms for digital logic circuit design has resulted in reduced architecture, greater speed, lower power consumption, and improved operational efficiency.

Keywords:-VLSI; Nikhilam, Vedic mathematics, Urdhva Tiryakbhyam, Yavadunam,  Ekanyunena Purvena, Anurupyena.

Authors:-Tasmai Choudhary, Gurbir Bhatia

Abstract:-As chip manufacturing technology rapidly advances, shrinking device size and performance, the LFSR (Linear Feedback Shift Register) is incorporated in layout level, developing the low power consumption chip utilising contemporary CMOS, sub-micrometer designing tools. Thus, the LFSR counter can be a new trend setter in cryptography, as well as advantageous when compared to the GRAY & BINARY counters and a number of other applications. Using the Microwind CMOS layout tool, this article analyses three designs in terms of hardware implementation, CMOS layout, and power consumption. As a result, it offers a solution for a low power architectural implementation of LFSR in CMOS VLSI.

Keywrds:-Layout level, Chip technology, LFSR, Pass transistor.

Authors:-Anjum A. Sanadi, Mehar I. Bagsar, Noor S. Attar, V.B.Kamble

Abstract:-Nowadays most of peoples use motor for their respective works. Most of the companies use ac motors in AC Motor there is switches that are on and off if the user press the on button then the work will start and if user presses off button then working will stop there is need the arson will present in that place to remove this drawback we implement some features in our project ,such as we create a automatic based motor we create one application to control the motor in case the person is not present in that place then through the application the person can do their task easily. It will control the motor from anywhere.

Keywords:-GSM, Microcontroller, starter and power supply

 

Authors:-Dr. Prashant Prabhakar, Deepak Pandey

Abstract:-Historically, VLSI designers have focused on increasing speed and reducing the area of digital systems. Low power design reduces cooling cost is and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. Yet, high performance is still the main criterion for most digital systems, which may not be sacrificed to achieve low power dissipation. This study covers two logic families; namely CMOS and CPL presents low power digital VLSI design methodologies. To verify the qualitative analysis, three gates AND, OR, MUX are implemented using two  logic families: CMOS,CPL. On the block level, a 16 bit CLA adder is used as a test vehicle to evaluate the performance of the above logic families. Then the factors like performance, Power of different CMOS logic styles is then analysed and simulated. A 16bit CLA adder is designed, simulated, using 0.6µm CMOS technology.

Keywords:-Power Dissipation, CMOS, CPL, CLA Adder.

Authors:- Dr. Vasudha Damle, Divya Sharma

Abstract:- Worked in Self-Test plays an important role in VLSI circuit testing. To test the Circuit under Test, test designs developed with the design generator are used. Regular test design age techniques include Reconfigurable Johnson Counter and LFSR, which are required in the interaction between progressive test vectors. A Reconfigurable Johnson Counter and Accumulator is used to develop a Modern Low Power test design. For battery-powered devices, a Low Power Consumption device is essential. The system for providing BIST test vectors is written in VHDL, and simulations were carried out with ModelSim 10.0b.

Keywords:- Test Pattern Generator (TPG), Built-in-self-test (BIST), Multiple Single Input Change Vector (MSIC), VHDL

Authors:-Dr. Parth Chauhan, Gaurav Patel, Hardik Parmar

Abstract:- In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

Keywords:-VLSI Design, CMOS, Variable Body Biasing, Reduce Static Power

Authors:- Parmanand Patel, Kuldeep Tyagi

Abstract:-In order to decrease the power dissipation in ASIC design, Multi-voltage design techniques such as Power gating, Clock gating, Power down mode, Multi-threshold, etc. are employed. To help designers verify the correct implementation of these low power design techniques, Multi-voltage Rule Check is used. The implementation of different Multi-voltage design elements such as Isolation Cell, Level Shifter Cell, and Retention Cell and power aware design is explained using Unified power format (UPF). And in the design process from Register- transfer level (RTL) to Graphic Database System (GDSII) various changes are made to the netlist to make it easily testable, to satisfy the timing constraints, to optimally place and route the design. These processes introduce variations in the netlist, which must be checked to make sure that its functionality has not changed. So Formal Verification is performed to confirm that Golden netlist (Reference) and revised netlist are equivalent at different phases, example Synthesis, Design for Testability (DFT), Place and route. This paper discusses the different mathematical algorithms underlying formal Verification such as Binary decision diagram and Satisfiability solvers. It provides a detailed review of both formal verification and multi-voltage rule check.

Keywords:-Power gating, clock gating, unified power format, binary decision diagram, satisfiability solvers.

Author:- Shreya Saini

Abstract:-A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using VLSI technology. The designed counter can be used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The propose circuit will be faster than conventional circuit as it will be a fast reset operation. The circuit will be consuming less power as it prevents short circuit power consumption.

Keywords:-VLSI Technology, PLL, PFD, VCO, D-ff

Authors:-Dr. Prashant Shekhar, Mrutyunjay Rout, Ashish Kumar

Abstract:-Low power operation has become more crucial in VLSI design as technology scales. SRAM makes up a substantial component of current VLSI designs, hence attempts are being made to create low power SRAM in many methods. This paper explores multiple existing SRAM architectures, each with a different number of transistors. This research examines different designs and compares them based on metrics such as power dissipation, access time, stability, and power delay product. Each SRAM design has a distinct read/write process and so produces various results. When simulation results produced on 45nm environment using Microwind tool were compared, it was discovered that 12T SRAM has higher performance in terms of power dissipation and power dealy product but high access time than other current SRAM cells.

Keywords:-Static Random-Access Memory (SRAM), Low Power, Leakage Power, Static and Dynamic Power, Swing Voltage 

Authors:-Dr. Kumari Namrata, Puja Srivastava

Abstract:-The major goal of this article is to persuade the rider to wear his or her helmet the entire journey. Given the expanding number of motorcycles in our country and throughout the world, the record of injuries happening each year is obvious. In most cases, the rider suffered from head and brain injuries, which contributed to the fatality, which has thrown light on the situation. To reduce the breadth of hits, the rider must be required to wear a helmet guard. The study focuses on the methods that may be used to reduce the influence of impacts. The research focuses on a method for reducing the impact of roadways, which may be introduced with injuries. In this research, we suggest constructing a framework that can be introduced by placing it on a bike that works with the headgear that is worn to persuade the biker to do this: don your helmet before driving your motorbike.

Keywords:-Helmet, Safety, Sensor, Vehicle, Drunk driving, Intelligent system, Accident

Authors:-DR. S. Nidarshna, Mayuri Baruah

Abstract:-This paper discusses the implementation of harmonic distortion in distribution systems using a combination of active and passive filters. The active filter is used to minimise the amount of distortion in the output. A boost converter is used to boost the voltage. This boost converter is linked to the inverter, which is built with a MOSFET as a switch. In practise, the pulses for the inverter are provided by the Arduino control. The overall harmonics distortion is decreased to within the allowable level by employing this hybrid technique. The MATLAB simulink is used to simulate this proposed approach. Initially, quick fourier transform may be discovered to reduce harmonics. However, developing technologies like as Arduino control have shown to be easy and cost-effective in carrying out the same work successfully.

Keywords:-Arduino. VLSI, harmonics, THD, MATLAB

Authors:-Bongurala Simon, Sheba Rivy Gangadhar

Abstract:-For a VLSI design, the three most critical performance factors are logic latency, chip size, and power consumption. The VLSI design of a 16-bit ALU is discussed in this study, and it is optimised in terms of performance, power consumption, and chip size. Several logic families were employed in the construction of various logic modules used in the design of a 16 BIT ALU. The logic family chosen for each module is determined by characteristics like as speed and power consumption offered by the individual logic family. The adder circuit is the most important part of an ALU's arithmetic operations. This research study conducts a full examination of the several possible adder circuit layouts, and the best-fitting one is chosen for the construction of the needed ALU. To make the greatest ALU, Carry Skip Adder is used. By the conclusion of this article, a 16-bit ALU will have been created that displays several logic families such as CMOS for basic operations and pseudo-NMOS for advanced logic families.

Keywords:-NMOS, and VLSI, Design of CMOS, ALU,Adders

Authors:-Supriya Rathode, Lalita Kumari

Abstract:-We will learn how to utilise VHDL to develop a low power ALU in this paper. Following Moore's law, developments in VLSI technology have allowed for a three-year doubling in component density on a silicon chip. As the basic function of a transistor has improved, designs may now be realised with fewer transistors and fewer interconnections. Many integrated circuits with traditional CMOS technology that use multi-input floating gate MOSFETs have been disclosed in the literature. The proposed ALU architecture is more efficient as a consequence of the use of modern VLSI technology.

Keywords:-VHDL, VLSI, ALU, CMOS, 4-BIT LOW POWER

Authors: Dr. S. Karthikeyan, Ms. Anindita Ghosh

Abstract: Clock Tree Synthesis (CTS) is a critical stage inthe physical design flow of Very Large Scale Integration (VLSI) circuits, directly influencing performance, power consumption, and functional reliability. With the continuous scaling of semiconductor technology nodes and increasing design complexity, efficient clock distribution has emerged as a major challenge for digital integrated circuits. This paper presents a comprehensive study of clock tree synthesis and optimization techniques, focusing on design objectives such as minimizing clock skew, reducing insertion delay, managing power dissipation, and ensuring signal integrity. Classical clock distribution topologies, modern CTS algorithms, buffering strategies, and optimization approaches are discussed in detail. The paper also examines practical challenges such as process-voltage-temperature (PVT) variations, clock uncertainty, and design for testability. Through analytical discussion, comparative tables, and illustrative two-dimensional figures, this work aims to provide a structured understanding of CTS suitable for researchers and practicing VLSI engineers. The study concludes by highlighting emerging trends in clock network design for deep submicron and system-on-chip (SoC) architectures.

Keywords: Clock Tree Synthesis, Clock Skew, Clock Latency, VLSI Physical Design, Low-Power Design, Buffer Insertion, Timing Optimization