Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors: Kavya Singh, Ronit Sharma

Abstract:It is challenging to meet the speed and quality requirements of the IC physical structure due to the rapid increase in size and unpredictability of VLSI. Using active-logic reduction technology, we have presented an effective model for quick floor planning in VLSI top-down varied tiered physical structure stream. The disentangled show substitutes several unique modules in the netlist record with filling units that don't make sense. This technique can successfully reduce inner coherent units and predict whether a chip configuration achieves the best and squares execution with this floorplan, allowing a quick assessment of the floorplan's quality. Most importantly, it can maintain plan quality while speeding up the configuration process. All things considered, the results of six investigations show that the technique can reduce runtime by 6.2 times and memory by 2.8 times in VLSI varied levels physical layouts.

Keywords: VLSI, IC physical structure, Floor Planning, Multiple levels

Authors: Ravindra Bansal, Sagar Kumar

Abstract: The design of high-speed full adder circuits employing a novel CMOS mixed-mode logic family is presented in this study. The goal of this study is to offer a novel full adder design circuit paired with a current mode circuit in a single unit to build a full adder cell. This research also describes a high-speed hybrid majority function-based 1-bit complete adder with MOS capacitors (MOSCAP) and traditional static and dynamic CMOS logic circuits. The static Majority function (bridge) design style has a better degree of regularity and symmetric higher density than the traditional CMOS design style, as well as reduced power consumption due to the use of bridge transistors. This approach aids in decreasing digital circuit power consumption, propagation latency, and area while preserving the low complexity of mixed-mode logic designs. Dynamic CMOS circuits have advantages in terms of space, latency, and testability over static CMOS circuits. The simulation findings show that the newly developed adder circuits outperform the previously reported conventional CMOS, dynamic, and majority function adder circuits in terms of power, delay, power delay product (PDP), and energy-delay product (EDP). The design is done in Cadence Virtuoso Schematic Composer using UMC 0.18m process models at 1.8 V single-ended supply voltage, and simulations are performed on Spectre .

Keywords: Full adder, Majority-Not gate, Dynamic circuits, MOSCAP, Power-delay product (PDP), Very Large Scale Integrated (VLSI) Circuits, Current mode logic, Hybrid XOR-XNOR circuit, Bridge full adder.

Authors: Hiren Patel, Jinal Barot, Meena Chowdhury

Abstract: Electronic systems are an integral part of our daily life. Financial networks, public transit, telephone systems, power plants, and personal computers all use them. Complex VLSI (Very Large Scale Integration) integrated circuits are widely used in electronic systems. The design and manufacture of VLSI systems are the focus of first electronic design automation. Physical Design is the next crucial phase in the creation of a VLSI circuit. A logical representation of the system under design is used as the input to the physical design. The layout of a physical package that implements the logical representation ideally or almost optimally is the output of this stage. Physical design challenges are large-scale and combinatorial in nature. In the battle for fundamental necessities, Darwin noted that as new variants are introduced into a population with each new generation, the less-fit individuals tend go extinct. Species evolve as a result of the survival of the fittest concept. The goal of Genetic Algorithms (GA) is to identify the best possible solution to a problem. Because GAs are heuristic methods that can also operate as optimizers, they cannot promise that they will discover the best answer, but they can find acceptable solutions to a wide range of issues. This comprehensive work examines the common characteristics of exceptional contributions to Efficient Algorithms for VLSI Physical Design.

Keywords: VLSI Physical Design, Genetic Algorithms, Electronic Design Automation (EDA), VLSI circuit

Authors: Dr. Rishabh Kulkarni, Deepanjali Verma

Abstract: With the advent of new technologies and advancement in medical science we are trying to process the information artificially as our biological system performs inside our body. Artificial intelligence through a biological word is realized based on mathematical equations and artificial neurons. Our main focus is on the implementation of Neural Network Architecture (NNA) with on a chip learning in analog VLSI for generic signal processing applications. In the proposed paper analog components like Gilbert Cell Multiplier (GCM), Neuron activation Function (NAF) are used to implement artificial NNA. The analog components used are comprises of multipliers and adders’ along with the tan-sigmoid function circuit using MOS transistor in subthreshold region. This neural architecture is trained using Back propagation (BP) algorithm in analog domain with new techniques of weight storage. Layout design and verification of the proposed design is carried out using Tanner EDA 14.1 tool and synopsys Tspice. The technology used in designing the layouts is MOSIS/HP 0.5u SCN3M, Tight Metal.

Keywords: Signal Processing, Artificial Intelligence, Neural Network, Circuit

Authors: Dr. Manoj K. Deshmukh, Dr. Ritu Chatterjee

Abstract: As VLSI technology scales into deep submicron and FinFET nodes, thermal management becomes a critical concern affecting performance, reliability, and device lifetime. High-power densities lead to hotspots, increasing leakage currents and accelerating device degradation. Thermal-aware design techniques integrate simulation, analysis, and optimization during VLSI design to mitigate temperature-induced performance losses. This paper reviews the state-of-the-art thermal-aware design methodologies, explores simulation and analysis tools, discusses challenges such as hotspot prediction and thermal coupling, and highlights research opportunities in multi-physics co-simulation, machine learning-based thermal prediction, and power-aware floorplanning.

Keywords: Thermal-aware design, VLSI, Hotspots, Simulation tools, CAD, Power dissipation, Reliability.

Authors: Dr. Rajesh K. Iyer, Dr. Ananya Mukherjee

Abstract: With the increasing integration density and complexity of Very Large Scale Integration (VLSI) circuits, security vulnerabilities at the hardware level have become a significant concern. Hardware Trojans—malicious modifications of integrated circuits—pose threats to confidentiality, integrity, and availability of electronic systems. Security-aware VLSI design integrates detection, prevention, and mitigation strategies during the design and verification phase to safeguard against these threats. Modern Computer-Aided Design (CAD) tools enable designers to incorporate security checks, apply anomaly detection, and enforce design rules that minimize Trojan insertion risk. This paper explores security-aware VLSI design methodologies, reviews CAD tool capabilities for Trojan prevention, evaluates design flow integration, and provides recommendations for secure VLSI implementations.

Keywords: Hardware Trojans, Security-Aware Design, VLSI, CAD Tools, IC Security, Trojan Detection.

Authors: Dr. V. Balasubramanian, Ms. Riya Mukherjee

Abstract: Power, Performance, and Area (PPA) optimization has emerged as a central objective in modern VLSI design due to aggressive technology scaling, increasing system complexity, and stringent market-driven constraints. Achieving an optimal balance among these three conflicting metrics is essential for designing high-performance, energy-efficient, and cost-effective integrated circuits. Advanced VLSI Computer-Aided Design (CAD) tools play a critical role in enabling PPA optimization through automated analysis, optimization algorithms, and multi-objective trade-off exploration. This paper presents a comprehensive study of PPA optimization methodologies using modern VLSI CAD tools. The discussion includes PPA fundamentals, optimization challenges at nanometer technologies, CAD-driven techniques at various design stages, and emerging trends in multi-objective optimization. Tables and conceptual figures are used to illustrate optimization strategies and trade-offs. The paper concludes by highlighting future directions in PPA-aware VLSI design automation.

Keywords: PPA Optimization, VLSI CAD Tools, Power Optimization, Performance Enhancement, Area Reduction, Design Automation

Authors:Aruna Rao B P, Dr. Kiran Agarwal Gupta

Abstract:With the development of on-chip manufacturing technologies and the requirements of high-Speed communication and the core count is growing quickly in Chip Multi/Many-core Processors (CMPs) and Multiprocessor System-on-Chip (MPSoC) to support larger scale parallel execution. Network-on-Chip (NoC) has become necessary to meet the high-speed requirement for CMPs and MPSoCs in addressing the communication challenge. In this paper an attempt is made to make a survey on problems facing high-performance NoC designs for IOs.

Keywords:3D NOC, IO Architectures, Multiprocessor System-on-Chip (MPSoC), Network-on-Chip (NoC)

Authors:Ashutosh Singh, Khushi Sharma, Satyendra Kumar Gupta

Abstract:This project implement a new home automation system in which Wi-Fi technology is used as a network infrastructure connecting through Adafruit IO. The system which we used consist of two part; the first part is the server (web server), which presents system core that manages, controls, and monitors users’ home where he/she implement. Users and system administrator can locally (LAN) or remotely (internet) manages and control system code.  Second part is hardware interfacing module, which provides appropriate interface to sensors and actuator of home automation system which we used. Most of available home automation system in the market the proposed system is scalable that one server can manage many hardware interface modules as long as it exists on Wi-Fi network coverage. System supports a wide range of home automation devices like power management components, and security components. The system which we proposed is better from the scalability and flexibility point of view than the commercially available home automation systems.

Keywords: Wi-Fi Network, Home Automation, Power Management Components, Security Components

Authors: Dr. P. Ramesh Kumar, Ms. Sayantani Dutta

Abstract: Reliability has become a critical design objective in modern VLSI systems due to aggressive technology scaling, higher integration density, and prolonged operational lifetimes. Advanced nanometer technologies are increasingly susceptible to process variations and aging mechanisms that degrade circuit performance over time. These effects can lead to timing failures, increased power consumption, and reduced product lifetime if not properly addressed during the design phase. Modern VLSI design tools provide sophisticated analysis and optimization capabilities to model, predict, and mitigate reliability issues. This paper presents a comprehensive study of VLSI design for reliability with a focus on tool-based analysis of process variations and aging effects. The paper discusses key reliability challenges, modeling techniques, CAD tool support, and design methodologies for ensuring robust and reliable VLSI circuits. Tables and conceptual figures are included to illustrate reliability phenomena and analysis workflows. The paper concludes by outlining future trends in reliability-aware VLSI design automation.

Keywords: VLSI Reliability, Process Variations, Aging Effects, CAD Tools, Timing Degradation, Design Automation

Authors: Dr. S. Karthikeyan, Ms. Ananya Ghosh

Abstract: System-on-Chip (SoC) design has emerged as the backbone of modern electronic systems, integrating multiple heterogeneous components such as processors, memories, interconnects, and peripherals on a single silicon die. While this integration enables high performance and low power consumption, it also introduces significant verification challenges. Functional correctness, timing closure, power integrity, and reliability must be ensured across complex hardware-software interactions. Verification today accounts for more than 60–70% of total SoC development time, making it a critical bottleneck in time-to-market. This paper presents a comprehensive analysis of the major verification challenges encountered in contemporary SoC design flows and discusses tool-based solutions that address these challenges. Simulation-based verification, formal verification, emulation, and FPGA prototyping are examined in detail, along with emerging methodologies such as Universal Verification Methodology (UVM), assertion-based verification, and coverage-driven verification. The paper also highlights the role of commercial electronic design automation (EDA) tools and open-source verification frameworks. Case studies, comparative tables, and illustrative figures are included to provide clarity. Finally, future trends such as AI-assisted verification and shift-left verification strategies are discussed, emphasizing their potential to improve verification efficiency and reliability.

Keywords: System-on-Chip, SoC verification, functional verification, EDA tools, UVM, formal verification

Authors: Dr. K. Prakash, Ms. Moumita Das

Abstract: Static Timing Analysis (STA) is a fundamental sign-off methodology used to verify the timing correctness of synchronous VLSI circuits without relying on exhaustive simulation. As modern integrated circuits operate at increasingly higher frequencies and advanced technology nodes, timing margins continue to shrink, making accurate and efficient timing verification essential. STA tools evaluate the worst-case timing behavior of all signal paths in a design under multiple process, voltage, and temperature conditions. This paper presents a comprehensive study of Static Timing Analysis tools for high-performance VLSI circuits. The discussion includes STA fundamentals, timing models, analysis methodologies, challenges at nanometer technologies, and advanced optimization techniques integrated into modern STA tools. Tables and conceptual figures are provided to illustrate timing paths, constraint handling, and analysis modes. The paper concludes by highlighting emerging trends and future directions in STA for next-generation VLSI systems.

Keywords: Static Timing Analysis, VLSI Timing Closure, High-Performance Circuits, Timing Verification, EDA Tools

Authors: Dr. Anand R. Kulkarni, Dr. Meera S. Chatterjee

Abstract: As VLSI technology scales into the deep submicron (DSM) regime, the accuracy and reliability of physical design verification and parasitic extraction become increasingly critical. Deep submicron effects, such as short-channel phenomena, wire delays, crosstalk, and leakage currents, can significantly impact circuit performance and yield. Physical verification tools ensure adherence to design rules, electrical constraints, and layout integrity, while parasitic extraction tools model resistive, capacitive, and inductive effects arising from interconnect structures. This paper explores the role of physical verification and parasitic extraction in DSM VLSI design, examines modern EDA tools supporting these tasks, provides comparative analyses of tool capabilities, and presents a framework for integrating these tools into an optimized design flow.

Keywords: Physical verification, parasitic extraction, DSM, VLSI, DRC, LVS, RC extraction, crosstalk.

Author:-Dr. S. Balaji, Ms. Rituparna Ghosh

Abstract:-Physical design is a critical phase in the VLSI design flow, directly influencing the power, performance, and area (PPA) characteristics of an integrated circuit. With continuous technology scaling and increasing design complexity, conventional physical design techniques face challenges in achieving optimal results within reasonable turnaround times. Advanced VLSI CAD tools have introduced sophisticated optimization techniques to address issues related to placement congestion, routing complexity, timing closure, power dissipation, and manufacturability. This paper presents a comprehensive study of physical design optimization techniques implemented in modern VLSI CAD tools. The paper discusses key stages of physical design including floorplanning, placement, clock tree synthesis, routing, and post-route optimization. Various algorithmic approaches such as heuristic optimization, analytical methods, and data-driven techniques are examined. Comparative analysis through tables and conceptual figures highlights the effectiveness of these techniques in improving design quality and productivity. The paper concludes by identifying current challenges and future research directions in physical design automation.

Keywords: Physical Design, VLSI CAD Tools, Placement Optimization, Routing Techniques, Timing Closure, Power Optimization

Authors: Dr. Saurabh R. Patil, Dr. Priyanka Banerjee

Abstract: Open-source VLSI design tools have emerged as an accessible alternative to commercial Electronic Design Automation (EDA) software, facilitating education, research, and low-cost prototyping. These tools provide a platform for RTL design, synthesis, simulation, verification, and layout, often with active community support. Despite their advantages, open-source tools face limitations in scalability, process-node support, and industrial readiness. This paper provides a comprehensive review of current open-source VLSI tools, evaluates their capabilities and constraints, and identifies research opportunities for advancing open-source EDA ecosystems. It also presents case studies illustrating their application in academic and low-cost industrial environments.

Keywords: Open-source VLSI tools, RTL synthesis, Digital IC design, Verification, Layout, EDA research.

Authors: Dr. Rohan S. Patil, Dr. Nandita Roy

Abstract: The growing demand for energy-efficient integrated circuits has brought low-voltage and near-threshold VLSI design to the forefront of research. Operating at supply voltages near or below the transistor threshold reduces dynamic and static power consumption but introduces challenges such as timing variability, increased sensitivity to process variations, and reduced noise margins. Tool-based optimization using modern Electronic Design Automation (EDA) software enables designers to systematically address these challenges. This paper explores the principles of low-voltage and near-threshold design, analyzes CAD tool capabilities for timing optimization, voltage scaling, and reliability assurance, and discusses limitations and emerging research opportunities in this domain.

Keywords: Low-voltage VLSI, Near-threshold computing, EDA tools, Timing optimization, Power reduction, Reliability.

Authors: Dr. P. Karthikeyan, Ms. Debasmita Das

Abstract: Power consumption has emerged as one of the most critical constraints in modern VLSI system design due to the widespread adoption of portable, battery-operated, and high-density electronic devices. As technology scales down to deep submicron and nanometer regimes, power dissipation issues such as dynamic power, leakage power, and static power increasingly dominate design considerations. Electronic Design Automation (EDA) tools play a vital role in enabling designers to implement low-power VLSI design methodologies efficiently across the design flow. This paper presents a comprehensive study of low-power VLSI design methodologies supported by modern EDA tool flows. Techniques spanning architectural, logic, circuit, and physical design levels are discussed, with emphasis on power-aware synthesis, clock gating, multi-voltage design, power gating, and dynamic power management. Comparative analyses using tables and conceptual figures demonstrate the effectiveness of these methodologies in reducing power consumption while maintaining performance and area constraints. The paper concludes by outlining current challenges and future trends in low-power VLSI automation.

Keywords: Low-Power VLSI Design, EDA Tool Flows, Power Optimization, Clock Gating, Multi-Voltage Design, Leakage Reduction

Abstract: Field Programmable Gate Array (FPGA)-based prototyping has become a vital technique for validating Very Large Scale Integration (VLSI) systems before silicon fabrication. As VLSI designs grow in complexity, incorporating multi-core processors, high-speed interconnects, and extensive peripheral subsystems, traditional simulation-based verification alone is no longer sufficient. FPGA-based prototyping bridges the gap between slow, detailed simulations and costly post-silicon debugging by enabling near real-time execution of hardware designs. This paper presents a comprehensive study of FPGA-based prototyping tools used for VLSI system validation. It discusses the motivations for FPGA prototyping, architectural considerations, tool flows, and integration challenges. Commercial and open-source prototyping platforms are analyzed, along with methodologies for design partitioning, timing closure, and hardware-software co-validation. Comparative tables and illustrative figures are included to enhance understanding. The paper concludes by highlighting emerging trends such as hybrid emulation–FPGA platforms and AI-assisted prototyping flows, emphasizing their role in reducing time-to-market and improving design confidence.

Keywords: FPGA prototyping, VLSI validation, hardware-software co-design, system verification, design prototyping

Authors: Dr. Haripriya R. Menon, Dr. Subhashis Roy

Abstract: Advances in semiconductor integration have driven the evolution of three‑dimensional integrated circuits (3D ICs) and through‑silicon vias (TSVs) as key technologies for next‑generation Very Large Scale Integration (VLSI). These architectures promise reduced interconnect delay, improved performance, and higher integration density compared to traditional planar designs. However, the complexity of 3D stacking and TSVs imposes significant challenges on design, verification, and manufacturing test flows. Electronic Design Automation (EDA) tools have adapted to these paradigms by incorporating specialized features for physical design, thermal analysis, signal integrity, and testability in 3D/TSV systems. This paper provides a comprehensive study of EDA support for 3D IC and TSV‑based VLSI technologies, evaluates commercial and research‑grade tools, presents comparative analyses, and outlines ongoing challenges and future directions.

Keywords: 3D IC, EDA tools, TSV, VLSI, thermal analysis, physical design, design for testability.

Authors: K Uday Kumar Reddy, K Sainadh Singh, Dr. N Bhoopal

Abstract: In  recent  years,  the  development  in  the  deregulated  electricity  market  structure  increases  the number  of  market  participants  thereby,  makes  the  market  more  competitive.  Therefore,  it  is important  for  the  system  operator  to  determine  fast  and  accurate  static  available  transfer capability  (S-ATC)  of  the  system  to  provide  secure  electricity  power  wheeling.    This  paper proposes  the  fast  assessment  of  S-ATC  in  the  deregulated  environment  by  eliminating  the Contingency  pre-screening  process.  Application  of  Real  coded  genetic  algorithm  (RGA)  is  used as  a  tool  in  determining  S-ATC  without  finding  severe  contingencies.    The  effectiveness  of  the proposed  method  of  ATC  assessment  is  analysed  by  carry  out  different  bilateral/multilateral wheeling  transactions  on  Sample  six  bus  system  and  it  is  accuracy  compared  with  the Conventional Repeated Power flow Method.

Keywords: Component; Formatting; Style; Styling; Insert 

Authors: Dr. Kunal R. Deshpande, Dr. Ananya Mitra

Abstract: Application-Specific Integrated Circuit (ASIC) design involves a complex flow from high-level RTL design to final GDSII layout. EDA tool flows facilitate the systematic design, verification, and optimization of ASICs, ensuring functional correctness, timing closure, power efficiency, and manufacturability. This paper provides a comprehensive review of EDA tool flows for ASIC design, detailing each stage from RTL synthesis, functional simulation, and timing analysis, to placement, routing, verification, and GDSII generation. The paper also discusses challenges in tool integration, multi-corner analysis, and optimization, and highlights recent research directions in automation, AI-assisted design, and open-source flows.

Keywords: ASIC design, EDA tools, RTL-to-GDSII flow, synthesis, placement and routing, verification, CAD tools.

Authors: Nisha O. S, Dr. K. Siva Sankar

Abstract: Today’s submicron VLSI technology has been emerged as integration of many VLSI ICs into a single Si Chip called System-on-Chip (SoC). The SoC architecture normally contains multiple processors along with either separate or centralized memory blocks as its core elements as well as many noncore elements. Embedded RAMs are those whose address, data, and read/write controls cannot be directly controlled or observed through the chip’s 1/0 pins. Testing these memories, which are incorporated on a large percentage of VLSI devices are harder just because of the lack of controllability of its inputs and observe ability of its outputs. Testing such RAMs is the main objective of this paper. It is challenging to test embedded RAMs, and hence we will discuss techniques - design for testability (DFT) and built-in self-test (BIST), which help in improving the testability of these RAMs.

Keywords: Built-In Self-Test (BIST), March Algorithm, Switching Factor

Authors: Prakash Kerur, Dr. R.L. Chakrasali

Authors: Solar energy is inexhaustible, available abundant in nature and free from pollution. The solar photovoltaic (PV) systems are a perfect solution for power requirement urban residential areas since the system is noiseless. The main problem with solar energy is its intermittency. However, sometimes during clear days the solar panels generate surplus power beyond the needs. At these times, the surplus power is exported into the main utility grid. With increase of renewable energy sources causes various problems of grid integration to export the surplus power. The concept of digital grid (DG) and bi-directional smart meters are the solution for these problems. The digital grid” where a wide-area synchronized power system is sub divided into smaller or medium sized power systems. Subdivided grids called “digital grid cells” are connected together asynchronously via “digital grid routers”. The DGR is a multi-terminal AC/DC/AC power conversion device. In order to construct a DG, bi-directional power flow and asynchronous interconnection of many distributed solar roof tops. If the solar PV panel produces surplus power, then it has to be supplied to the grid and the exported surplus power must be accounted. The smart energy meter has to account for imported power from the grid to consumer system and the exported power from the consumer system to grid. In this paper Digital grid router (DGR) and smart meter combination are discussed.

Keywords: Digital Grid Router (DGR), Smart meter, Bi-directional power flow, Renewable Energy Sources

Authors: K Uday Kumar Reddy, K Sainadh Singh, Dr. N Bhoopal

Abstract: This paper   presents   a   new   way   to   design   PID controller for both integer order and fractional order with a time delay for a typical interacting cylindrical tank system using MATLAB FOMCON toolbox.  Here,  our  work  aims  to  study  the performance characteristics of integer order and fractional order PID  controller  on  the  current  integer  order  plant  obtaining minimum  objective  function  by Nelder –Mead optimization technique  with  different  performance  metrics  ISE,  ITSE  and IAE.  Next  our  work  shows  to  make comparison  between integer order  PID  controller  based  on  AMIGO  model  performance and fractional  order  PID  controller  on  time  domain  characteristics. The proposed  method  aims  finally  to  analyse  overall  desired performance  on  fractional  order  PID  controller  by  adding  two extra  degrees  of  freedom  over  the  integer  order  PID  controller with different performance criteria.

Keywords: Coupled tank,    AMIGOIO controller, FO controller, Nelder-Mead optimization, FOMCON toolbox

Authors: Dr. Raghavendra S. Kumar,Dr. Priyanka Banerjee

Abstract: Design for Testability (DFT) has emerged as a critical approach in the field of Very Large Scale Integration (VLSI) systems to ensure efficient testing and fault detection. With increasing circuit complexity and integration density, traditional testing methods have become insufficient to guarantee the reliability of integrated circuits (ICs). DFT techniques such as scan design, built-in self-test (BIST), and boundary scan significantly improve test coverage while reducing test time and cost. This paper provides a comprehensive review of DFT techniques in VLSI, discusses the tools used for implementing and analyzing these techniques, and presents comparative analyses supported by simulation results. A detailed framework for applying DFT in modern VLSI designs is also proposed, highlighting the trade-offs between area, performance, and testability.

Keywords: DFT, VLSI, Scan Design, BIST, Fault Coverage, Testing Tools.