Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors: Nisha O. S, Dr. K. Siva Sankar

Abstract: Today’s submicron VLSI technology has been emerged as integration of many VLSI ICs into a single Si Chip called System-on-Chip (SoC). The SoC architecture normally contains multiple processors along with either separate or centralized memory blocks as its core elements as well as many noncore elements. Embedded RAMs are those whose address, data, and read/write controls cannot be directly controlled or observed through the chip’s 1/0 pins. Testing these memories, which are incorporated on a large percentage of VLSI devices are harder just because of the lack of controllability of its inputs and observe ability of its outputs. Testing such RAMs is the main objective of this paper. It is challenging to test embedded RAMs, and hence we will discuss techniques - design for testability (DFT) and built-in self-test (BIST), which help in improving the testability of these RAMs.

Keywords: Built-In Self-Test (BIST), March Algorithm, Switching Factor