Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors:-Hitlendra Pratap Singh , Dr. G.S. Virdi

Abstract:-An analytical delay model is proposed for RLC modeled high speed on-chip VLSI interconnects based on a second order approximate transfer function in DSM technology environment. The proposed analytical delay model is almost independent of the ratio of V_o/V_i (output voltage to input voltage) and the driver resistance (R_D) has an impact on the delay correspondingly speed and reliability of the circuit gets affected. It is observed that real pole model provides better accuracy and is much faster than the complex pole model. An analytical delay model for RLC interconnect line with complex and real poles based on a second order approximation that considers the effect of inductance and incorporates ground capacitance. The impacts of driver/source resistance and output load capacitance have also been taken into account. For a wide range of driver, load, and interconnect line parameters the delay of the circuit model is calculated. It is observed that the average error rate of our developed models (both real and complex pole models) is within 10.49% and 10.14% with HSPICE simulation.

Keywords-Delay model, Transfer function, RLC Interconnect, complex poles, real poles