Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors: Dr. A. Natarajan, Ms. Ishita Paul

Abstract: Physical verification is a critical sign-off stage in the VLSI design flow, ensuring that a layout is both manufacturable and functionally equivalent to its intended design. Among physical verification tasks, Design Rule Checking (DRC) and Layout Versus Schematic (LVS) verification play a central role in preventing fabrication failures and functional mismatches. With the transition to nanometer and sub-nanometer technologies, the complexity of design rules and verification requirements has increased dramatically. Modern VLSI tools must handle complex geometric constraints, multi-patterning rules, and hierarchical designs while maintaining reasonable runtimes and accuracy. This paper presents a comprehensive study of DRC and LVS verification using modern VLSI tools. The paper discusses the fundamentals of DRC and LVS, evolving challenges at advanced technology nodes, and the role of contemporary EDA tools in automating physical verification. Comparative tables and conceptual figures are included to illustrate verification flows, error types, and optimization outcomes. The study concludes by highlighting current challenges and future trends in physical verification automation.

Keywords: Physical Verification, Design Rule Checking, Layout Versus Schematic, VLSI Tools, Nanometer Technologies, Sign-Off Verification