Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors: Sabita Thakur, P sreenivasan

Abstract: Functional verification has become the dominant cost and time factor in modern Very Large Scale Integration (VLSI) design cycles. With increasing design complexity, traditional verification methodologies struggle to provide sufficient coverage within reasonable schedules. Artificial Intelligence (AI) and Machine Learning (ML) techniques have recently emerged as promising solutions to accelerate verification tasks and automatically mine meaningful assertions from large simulation data. AI-accelerated verification improves test generation, bug detection, coverage closure, and regression optimization, while assertion mining enables automatic extraction of temporal properties from design behavior. This paper presents a comprehensive review of AI-driven verification methodologies and assertion mining techniques, highlighting their principles, workflows, benefits, and limitations. We discuss supervised, unsupervised, and reinforcement learning approaches applied to simulation-based and formal verification environments. A detailed comparison between conventional verification and AI-accelerated approaches is also provided. Challenges such as scalability, explainability, data quality, and industrial adoption are analyzed. Finally, future research directions toward trustworthy, hybrid AI-assisted verification frameworks are outlined.

Keywords: AI in VLSI, Functional Verification, Assertion Mining, Machine Learning, Formal Verification, Coverage Optimization