2021
No 45 (2021): Haptics and Electromyogram (EMG): Recent Advancements and Future Aspects for Enriched Haptic Experience
Authors:Â Shalini Mukhopadhyay, Jayendra Kumar, Ankita Rayon, Shalini Priya
Abstract:Â Haptic technology has enabled rapid advancements in human-computer interactions and has opened up a wider spectrum of applications such as gaming, interactive computing, robotics, medical equipment advancements and many more. The study of haptic devices is an emerging area of interest among researchers due to its close relation to the very widely explored domain of robotics and artificial intelligence. The various types of haptic feedback- tactile, kinesthetic, force feedbacks, have been utilized in different applications. The electromyogram (EMG) signal depicting the electrical activity of muscles has been utilized in haptic systems in the form of feedback, and there have been various developments in haptic devices as well as EMG signal processing in recent years. This study presents a brief review of the basic concepts of haptics, EMG, the recent advancements in these fields, and the present state of research applying the combination of haptics and EMG together to obtain enhanced outputs that can be utilized across various applications.
Keywords: Haptics, Tactile actuation, Kinesthetics, Force feedback, Electromyogram (EMG).
No 46 (2021): Performance Analysis of Barnacles Mating Optimization Algorithm and Black Widow Optimization Algorithm on Improved Pi-Si
Authors:Â T. Mathi Murugan, Dr. E. Baburaj
Abstract:Â The utilization of multilayer perception and feed forward network has limitations in the neural network, such as multi-layering and linear threshold unit for different engineering applications. Thus, higher-order neural networks were beneficial in performing non-linear mapping, which utilises the input units with the single layer for conquering the limitations of the conventional neural networks. The paper utilises a higher-order neural network known as the improved Pi-Sigma neural network coupled with the Barnacles Mating Optimization (BMO) algorithm and Black Widow Optimization (BWO) algorithm for developing an effective hybrid training algorithm for classification process with global and local searching abilities. For validating the performance of the proposed BMO-IPSNN and BWO-IPSNN algorithm, the algorithm was tested with different types of datasets obtained from UCI machine learning source, and then the algorithm was evaluated with the other existing algorithms such as PSO-PSNN, IPSNN, FFA-PSNN and PSNN. The result from the experiment concludes that the proposed algorithm gains superior performance for classification problems.
Keywords:Â Bio-inspired algorithms, Optimization, Classification, Neural networks
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No 47 (2021): Study and Design of Opamp based Bandgap Reference Circuit
Authors: Ankur Sah, Yalamanchili Vahini, Basanta Bhowmik
Abstract: The present paper concerns about a ï¬rst order bandgap reference circuit (BGR) employing a single-stage differential ampliï¬er and BJT. An external start-up circuit (based on the current mirror) is used to expedite the transistor switching faster and to avoid the non-stable state of BGR. The opamp has been designed to offer optimum gain suitable for the BGR. Temperature independence of BGR was achieved by superposition of the effect of CTAT and PTAT. Generation of constant voltage with temperature variation (-40oC to 125oC) has been conï¬rmed through an open-source simulation tool (NGSPICE). The simulation study reveals that the temperature coefï¬cient and the start-up time of the design were 78.8 ppm/oC and 12µs, respectively.
Keywords:Â Bandgap, PTAT, CTAT, opamp.
No 48 (2021): Design of Micro-Ring Resonator Based All Optical Signal Routers
Authors:Â Rakesh Choudhary, Sushanta Mahanty, Ajay Kumar, Rajiv Kumar, Basudeba Behera
Abstract:Â The analysis of digital circuits in optical field is one of the key aspects of emerging technologies. The proposed article shows the effective method for implementing the micro- ring resonator structure in all-optical signal routers. First of all, we explained in details how the resonator arrangement of the micro-ring resonator can be used in optical switching. This paper contains the detailed description and layout design of the all-optical signal router proposed. Finally, the theories suggested are tested with the MATLAB simulation software. The various fields of optical computing open up the door to a high-speed signal processing which has some important optical communication advantages like smaller size, lesser attenuation, wider bandwidth, lower cost computation and more immune to EMI.
Keywords: Micro-ring resonator, All-optical signal routers, Optical switching
No 49 (2021): Implementation of All-Optical Even Parity Checker Using the Micro-Ring Resonator Structure
Authors:Â Sushanta Mahanty, Rakesh Choudhary, Ajay Kumar, Rajiv Kumar, Basudeba Behera
Abstract: The Diverse field of all-optical computing technique provides the door of very efficient high-speed signal processing, which includes some considerable advantages of optical communication e. g. miniature size, secure transmission, less attenuation, greater bandwidth, and less computation time. The proposed paper describes the concept of switching activity of Micro-Ring resonator (MRR)and Further, the switching activity of MRRs is efficiently applied to implement the 4 bit all-optical even parity checker. The appropriate layout diagram along with the mathematical aspects of the proposed device is described in this paper. The discussed schemes are verified and simulated using MATLAB.
Keywords: MRR, All-optical logic gates, All-optical parity checker.
No 50 (2021): Performance Optimization of Digital Circuits using PTL and CMOS Technology
Authors:Â Prerna Gupta, Shruti Awasthi, ManinderBir Singh Gulshan
Abstract:Â The objective of this research paper is to analyze the various combinational circuit using PTL technology as well as CMOS technology. It mainly focuses on the characteristics of both the logic designs in terms of the power consumption, power supply, power dissipation and chip area. All the combinational and sequential circuits are designed using the LTSpice tool along with their layout designs using the MAGIC layout tool. Hence, all the circuits are analyzed using open-source simulators.
Keywords:Â Adders, Flip flop, PTL, CMOS, Power consumption, Power dissipation, Power supply and Chip area.
No 51 (2021): Different Parametric Analysis of One Port SAW Resonator using COMSOL
Authors:Â Baruna Kumar Turuk, Gyanabrata Sahoo, Aditya Kumar Nagmani, Basudeba Behera
Abstract:Â In this paper, a one-port SAW resonator with various operating frequencies is simulated using COMSOL Multiphysics. The resonator can be achieved in two ways one is a single IDT having a finite electrode over a piezoelectric substrate another is a short IDT with reflecting grating at the end of the IDT. SAW devices can be used as sensor and actuator delay line, signal processing unit, filter and resonators. Surface Acoustic Wave is one of the key components in an electronic circuit. A SAW is a mechanical wave, and this wave is excited on the piezoelectric substrate when a voltage is applied to the electrode. Distance between the two electrodes in the IDT decides the frequency of the propagating wave.
Keywords: SAW, Resonators, IDT, COMSOL Multiphysics.
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No 52 (2021): Functional Verification of DMA Controller of an Image Processing SoC
Authors: Shouvik Saha, Shalini Mukhopadhyay, Saurabh Bhokre, Basudeba Behera
Abstract:Â Technology in the field of VLSI is growing faster. After the advent of different standard hardware protocols& bus signal architectures, they are used for the interconnection of various modules on a System-on-a-Chip (SoC). In order to reduce the design time of the complete system, the SoC design became the most vital and integrated methodology. It has become challenging to verify those on-chip bus protocols as the traditional method is failing in the case of large and complex SoCs. In this paper, we are going to analyze the entire functionality of the DMA controller module of an image and video processing SoC. The DMA controller is based on AXI protocol, and so it is called AXI-DMA controller. A verification environment is built using Verilog and tested in Simics & have succeeded in verifying the AMBA AXI protocol, analyzing the read successfully and write operation for an incremental burst with saleable test bench architecture.
Keywords:Â AHB, APB, AXI, SoC (system-on-a-chip), VCS, Simics.
No 53 (2021): Simulation and Performance Analysis of Cascode Amplifiers in 90nm and 45nm Technology
Authors: C. S. Sajin, T. A. Shahul HameedÂ
Abstract: This paper presents the simulation of differential cascode amplifier, two-stage cascode amplifier and folded cascode amplifier in 90nm & 45nm, and its comparative review study with reported results. Cascode amplifiers render essential output impedance and diminish the impact of miller capacitance, thereby improving speed achievement. In this work, the performance parameters are optimized by respecting their tradeoffs, and the work aims at bandwidth enhancement. The bandwidth is raised by improving trans conductance and lowering the output capacitance. Here the circuit is simulated using cadence virtuoso tool and in gpdk technology. Amongst amplifiers simulated in this paper, the differential cascode amplifiers deliver well in terms of gain, and the folded cascode amplifiers manifest the best speed characteristics. The two-stage cascode amplifiers perform reasonably in terms of gain and frequency. The optimized simulation of differential cascode amplifiers in 45nm manifests 36 dB gain,15.8 MHz bandwidth, 300 MHz unity-gain bandwidth, and consumes very less power of 195nW. The two-stage cascode amplifier in 45nm exhibits 24.8 dB gain, 950MHz bandwidth and 6.5 GHz unity-gain bandwidth and these values prove the significance of the circuit in high- frequency applications. The folded cascode amplifier in 45nm results in frequency response with 3 dB frequency of 4.9 GHz and UGB of 18GHz.This value shows that the speed performance of folded cascode amplifier in 45 nm is superior over other simulated cascode amplifiers presented in this work and that reported in [1]. The simulated folded cascode amplifier in 45 nm consumes an area of 2.65µm x 2.65µm(7.03 µm2 ). It consumes 67µW from a 1V power supply.
Keywords:Â Folded Cascode Amplifier (FCA), Two Stage Cascode Amplifier(TSCA), Differential Cascode Amplifier (DCA), Unity Gain Bandwidth (UGB).
No 54 (2021): Optimization of ZnSnO/CIGS Solar Cell with the Incorporation of Cu2O-EBL Layer
Authors:Â Alisha Priya, Prashant Kumar, Shiva Nand Singh
Abstract:Â In this article, the study of CIGS solar cells is carried out by employing 1-dimensional numerical simulations using the simulator AFORS-HET. Here simulation of the conventional structure of Al/SLG/ZnO: Al/i-ZnO/ZnSnO/CIGS/Mo solar cell is done in which experimental values are used for the verification of the simulation. Also, a novel architecture is designed by incorporating the cuprous oxide (p-type Cu2O) layer as an electron blocking layer (EBL)at back-contact for the reduction of the minority carrier recombination loss. The parameters of the cell are optimized at different concentrations of doping and thickness to get better performance. The obtained efficiency of the proposed structure is raised by 9.62% in comparison to the experimental work.
Keywords:Â Cu2O, CIGS, EBL, BSF, CBD
No 55 (2021): Efficiency Improvement in Metal Oxide Gas Sensor Relays
Authors:Â Aditya Kumar Singh, Nikita Kar Chowdhury, Basanta Bhowmik
Abstract:Â Semiconductor metal oxides are widely used for different applications in different fields. In this review, we discuss various metal oxides like ZnO, SnO2, TiO2, WO3 and CuO that has different synthesis process where different characterizations are adopted. It also shows the variations and effect on different parameters of sensor device such as sensitivity, response and recovery time.
Keywords: Metal Oxides, Semiconductor, Characterization, Sensor, Synthesis.
No 56 (2021): Design and Simulation of All Optical NOT logic gate using Micro-ring Resonator
Authors:Â Niraj Kumar, Rakesh Choudhary, Sushanta Mahanty, Ajay Kumar
Abstract:Â Â All optical computing phenomena are considered the most meticulous and inventive approach to meet the ever-expanding demand of immense speed and rapid switching communication networks. The micro-ring resonator can be used as an elemental apparatus for designing various all-optical computing phenomena. This piece describes the able switching ability of a micro-ring resonator architecture. Further, this also explains the suitable technique for implementing an all-optical NOT logic gate, along with the switching action of a micro-ring resonator architecture with MATLAB simulation result. Lastly, the outcome of the recommended device is authenticated using the MATLAB simulation result. Optical switching activity to obtain the NOT logical functionality includes some additional advantages in an optical communication network. e.g., immunisation from electromagnetic interference, security to the signals, parallel computation, compactness.
Keywords: Optical logic gate, Micro-ring resonator, Optical NOT logic gate, Optical Switching.
No 57 (2021): New Electronic / Resistor Tunable Grounded Inductance Simulation Configuration
Authors:Â Priyanka Joshi, Rampriya Kumar, Ajay Roy, Mayank Srivastava
Abstract:Â In this research communication a novel electronically/resistor adjustable grounded inductance simulation con- figuration has been developed. This design is developed by employing two VDCCs (Voltage Differencing Current Convey- ors) along with three grounded resistances and one grounded capacitance. The developed configuration enjoys advantages like employment of only grounded capacitance and resistance, no need of matched active/passive components, availability of inductance value control through grounded resistances and bias currents (electronic adjustments) of used VDCCs, undeviated performance under non-ideal environment and small passive/active sensitivity index values. The utility of designed synthetic inductance has been validated through a second order band-pass filter designed employing it. To validate the theoretical/mathematical results, simulations in PSPICE environment have been executed employing CMOS based VDCCs.
Keywords: Electronic control, Resistance control, Synthetic inductor, VDCC).
No 58 (2021): Spiral Shaped Solid Core Photonic Crystal Fiber with Highly Nonlinear and Low Confinement Loss
Authors:Â Anand Kumar
Abstract:- Photonic crystal fibres (PCFs) is attracting more attention nowadays as a promising platform for communication chemical sensing and measurements. A spiral PCF structure is made of silica material is proposed where the core is defined as solid. Utilizing the finite element method (FEM) has numerically investigated waveguide properties. The PCF characteristics such as normalized frequency, mode field diameter, effective area, nonlinearity, and confinement loss are investigated. The ultra-low confinement loss is achieved at a 1.55μm wavelength. The high nonlinearity 7W-1km-1 at 1.55μm wavelength is achieved. The ultra-high birefringence 0.84065×10-2 is achieved at a 1.5 μm wavelength.
Keywords: -Â Photonic crystal fibre, confinement loss, nonlinear coefficient, effective area, normalized frequency.