No 50 (2021)

Performance Optimization of Digital Circuits using PTL and CMOS Technology

Authors: Prerna Gupta, Shruti Awasthi, ManinderBir Singh Gulshan

Abstract: The objective of this research paper is to analyze the various combinational circuit using PTL technology as well as CMOS technology. It mainly focuses on the characteristics of both the logic designs in terms of the power consumption, power supply, power dissipation and chip area. All the combinational and sequential circuits are designed using the LTSpice tool along with their layout designs using the MAGIC layout tool. Hence, all the circuits are analyzed using open-source simulators.

Keywords: Adders, Flip flop, PTL, CMOS, Power consumption, Power dissipation, Power supply and Chip area.

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