Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors: Udita Rawal, Mayank Verma

Abstract: 

Design for Testability (DFT) has become a critical aspect of Very Large Scale Integration (VLSI) design. As the complexity of integrated circuits (ICs) increases, ensuring their functionality through effective testing methods is
paramount. DFT techniques are incorporated during the design phase to simplify the testing process and enhance the detection of manufacturing defects. This paper explores various DFT strategies such as scan-based testing, built-in self-test (BIST), boundary scan, and automated test pattern
generation (ATPG). It also discusses the challenges, benefits, and future trendsM in DFT within the VLSI domain.

Keywords: Design for Testability (DFT), VLSI, Scan-Based Testing, Built-In Self-Test (BIST), Boundary Scan, Automated Test Pattern Generation (ATPG)