Journal of Research in VLSI Design Tools and Technology ISSN: 3139-2016 (Online)

Authors: Ananya Mehta, Raghavendra Singh, Nandita V. Joshi, Karthik M. Rao

Abstract: Three-dimensional integrated circuits (3D ICs) and advanced semiconductor packaging technologies have emerged as critical solutions to overcome the limitations of traditional two-dimensional (2D) scaling. Through-Silicon Via (TSV)-enabled vertical stacking offers improved bandwidth, reduced interconnect lengths, enhanced functionality, and superior power efficiency. As device geometries continue to shrink and heterogeneous integration becomes essential, 3D IC design flows and Electronic Design Automation (EDA) tools must evolve to handle new design, verification, and thermal challenges. This paper presents a comprehensive overview of the principles, architectures, packaging techniques, TSV fabrication methodologies, and design tools that
drive modern 3D IC development. It also discusses key challenges, recent advancements, and the potential scope of future research, providing a consolidated reference for engineers, researchers, and designers engaged in next-generation semiconductor integration.

Keywords: 3D IC, Through-Silicon Via, TSV Design Tools, Advanced Packaging, Heterogeneous Integration, 2.5D IC, Chiplet Architecture, Thermal Management, EDA Tools, Semiconductor Technology.