Journal of Power Electronics and Drives ISSN: 3139-1923 (Online)

Abstract

Current control systems and emulation systems (also known as Hardware-in the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications typically consist of a large number of components and interconnecting buses. These components typically include a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as an interconnect System-on-Chip (SoC) technology integrates a significant number of these functionalities into a single semiconductor chip. This provides the benefit of a decrease in both space and costs, in addition to an increase in the speed of communication within the company. These kinds of systems become increasingly significant not only for scientific study but also for applications in industry. The System-on-Chip (SoC) that serves as an example here combines a fast processor system (FPGA) with a Dual-Core ARM 9 hard processor system (HPS), and there are also fast interlinks between these individual components. For SoC systems to be able to provide real-time control and emulation, the accompanying software and firmware principles need to be carefully considered. This paper explains how to use the resources of the SoC in the most effective way possible and analyses the difficulties that are generated by the internal structure of the SoC. The utilisation of asymmetric multiprocessing is the primary concept here: One of the cores operates in hard real time using a bare-metal operating system. On the second core, a "real-time" Linux operating system handles service operations and communication respectively. The Field Programmable Gate Array (FPGA) is utilised for flexible process-oriented interfaces (such as A/D, D/A, and switching signals), quasi-hard-wired protection, and the exact timing of the real-time control cycle. This method of implementation is well known and is even occasionally proposed; but, to the best of the author's knowledge, it is only seldom put into practise and rarely documented within the context of demanding real-time control or emulation. In the article, the method of implementation is broken down in great detail, including the process interfaces, and the study also addresses the benefits and drawbacks of the selected idea. The outcomes of the measurements provide evidence of the solution's qualities.

Keywords: SoC, control, cache interference, multiprocessing