Journal of Power Electronics and Drives ISSN: 3139-1923 (Online)

Abstract

In this study, Wallace Tree Adders and FIFB, FIEB, and FISB Carry Save Adders are designed, Verilog-encoded, and simulated using Cadence Software. The implementation of adders takes place on CMOS chips with a 180 nm process. Power consumption, latency, silicon area, and dynamic power dissipation simulation results are compared. Both the Carry Save Adder and Wallace Tree Adder see a rise in the number of inputs, power consumed, silicon area, and latency. The suggested Wallace Tree Adder is shown to be more cost effective and a better solution for real-time applications than the typical CSA since it has a shorter delay, less power dissipation, and requires less silicon space.

Keywords: Verilog, Wallace tree based adders, Power consumption, Carry save adders, Silicon area, delay, Dynamic power dissipation