Journal of Power Electronics and Drives ISSN: 3139-1923 (Online)

Abstract

For high-end power-electronic applications, current control and emulation systems (also known as Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) often consist of a large number of components and interconnected buses. A microcontroller for communication and high-level control, a DSP for real time control, an FPGA section for quick parallel actions and data acquisition, multiport RAM structures, or bus systems as an interface are common components. A substantial number of these capabilities are integrated into a single semiconductor chip through System-on-Chip (SoC) technology. This has the advantage of saving space and money while also increasing the speed of communication inside the firm. These kind of systems are becoming increasingly important not just for scientific research but also for industrial applications. The System-on-Chip (SoC) used here combines a fast processor system (FPGA) with a Dual-Core ARM 9 hard processor system (HPS), with fast interconnects between these separate components. The supporting software and firmware concepts must be carefully studied for SoC systems to enable real-time control and emulation. This article describes how to use the SoC's resources as efficiently as possible and examines the issues caused by the SoC's internal structure. The fundamental principle here is the use of asymmetric multiprocessing: One of the cores runs a bare-metal operating system in hard real time. A "real-time" Linux operating system conducts service activities and communication on the second core. FPGAs are used for flexible process-oriented interfaces (such as A/D, D/A, and switching signals), quasi-hard-wired protection, and precise timing of the real-time control cycle. This implementation technique is well-known and is even occasionally proposed; but, to the best of the author's knowledge, it is only seldom used and rarely documented in the context of demanding real-time control or emulation. The technique of implementation is broken out in great length in the paper, including the process interfaces, and the research also examines the pros and cons of the chosen notion. The results of the measurements demonstrate the solution's properties.

Keywords: Multiprocessing, Control, Cache Interference, Soc