Authors: Aniket Sharma , Ravinder Jain
Abstract: RISC-V is an emerging open-source instruction set architecture (ISA) that has gained significant traction in the embedded systems domain due to its modularity, simplicity, and extensibility. As embedded workloads become more diverse and performance-constrained, optimizing the RISC-V ISA for such applications is critical to achieving low power consumption, high performance, and area efficiency. This review paper explores the current strategies for RISC-V ISA optimization targeted at embedded workloads. We examine architectural enhancements, instruction set extensions, compiler-level optimizations, and hardware-software co-design approaches. Additionally, we discuss case studies demonstrating energy efficiency improvements and performance gains in real-world embedded applications. Challenges, trade-offs, and future directions are also highlighted, providing a comprehensive reference for researchers and engineers working on RISC-V embedded systems.
Keywords: RISC-V, Embedded Systems, ISA Optimization, Instruction Set Extensions, Low Power, Performance Tuning, Compiler Optimization, Hardware-Software Co-Design
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