Authors: Tanushree Girkar, Sneha Nagar, Prof. H.R. Singh
Abstract: Speed of processor is the biggest issue nowadays. We live in a world where we are moving fast, hence to make our work easy, processors are designed which are getting more and more complex. This paper is about how we can reduce the overall time required for processing the input, For this purpose, we require some sort of mechanism that reduces the number of clock cycles. To this end, pipelining and subpipelinig is used. Generally, bubble pushing is used in pipelining to make the processor more efficient. The instruction sets used by the processor are very simple. The modeling of processor is done using verilog language for digital systems. The simulator used is Xilinx model simulator. Complex models are designed by behavioral modeling. The type of processor used is RISC. The processor is operational for 16 data bit, but it can be modified for 32 bits.
Keywords: Processor Pipelining, 16 bit Processor, Staged Pipelining, Pipelining Hazards
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