Authors:Â Shraddha Y. Swami, Jayashree S. Awati
Abstract:Â Reconfigurable device like FPGA, are capable of reducing execution times by making use of parallelism techniques in image processing algorithms. Implementation of highly parallel system architecture, Parallel access of large internal memory banks and optimization of processing element for different applications makes FPGA an ideal for image processing applications .Edge detection in an image processing helps to extract information from an image because edges in an image are consisting of meaningful features. So, significant information of an image can be extracted from edges. Sobel edge detection is gradient based edge detection method. Xilinx Spartan 3E FPGA kit is used to realize the Sobel edge detection filter. In VLSI area, power and delay are important design factors. These three factors depend upon each and every operation performing in an FPGA. Arithmetic and logic operations play an important role in digital circuits. A systems performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence optimizing the speed and area of the multiplier is a major design issue. This paper presents the implementation of Sobel Edge detection filter using Normal multiplier, Shift-Add multiplier and radix-4 Booth Multiplier and comparison of their results.
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