Authors:-Bhargavi B A, Dr. Roopa M
Abstract:-There has been an increasing concern about the growing vulnerability of future computing systems resulting errors in the underlying hardware. Providing reliability unlike conventional fault tolerant techniques, without additional resources is a critical challenge in deeply scaled CMOS and post CMOS era. Hence designing a reliable system with low overheads is very important. To tackle this challenge, we take the benefit of different intrinsic resilience of application domains such as multimedia, recognition, mining, search and analytics which produces acceptable outputs despite occasional approximate computations. In this paper as a new approach of performing approximate error checking at greatly reduced overhead is proposed. Stochastic Checkers are designed by using stochastic computing (SC). This checker has main benefit of using compact arithmetic elements. Additionally it is innately fault tolerant because of its distinctive encoding of numerical values. Hence by using necessary Binary To Stochastic (BTS) converter and Stochastic To Binary (STB) converter error checkers are designed. Further Triple Modular Redundancy[TMR] is proposed to depict the advantage of Stochastic Checker (StoCK), further both the proposed designs are explored and Simulation are carried out for both FIR filter and a equation, applications using Xilinx Vivado design suite, as compared with traditional fault tolerant technique while maintaining high fault coverage.
Full Issue
| View or download the full issue | PDF 86-99 |