International Journal of Research in Electrical, Electronics and Communication Engineering ISSN: 3107-8907 (Online)

Authors : D. Hadassah Rachel, G.Anjaneyulu

Abstract: The Latches and flip-flops are fundamental blocks for sequential circuits. In this paper, a new type of pulsed latches of is introduced. Its topology is depends on a push–pull final stage driven by two split paths with a conditional pulse generator, which differs in two circuit implementations which can be either shared (CSP3L) or not (CP3L).The concert for proposed topology is very fast and outperforms the familiar transmission gate pulsed latch (TGPL) and TGPL is taken as reference circuit. Hence the proposed pulsed latch has the highest performance yet reported. Accordingly, the proposed class of pulsed latches goes within the current state of the art and it is well suited for VLSI systems that require high performance. The designs are simulated in mentor graphic tools with a supply voltage of 0.8v at 130nm technology.

Keywords: -Flip-Flops (FFs), pulsed latches, Energy efficiency, energy-delay tradeoff, high speed, low power.