International Journal of Research in Electrical, Electronics and Communication Engineering ISSN: 3107-8907 (Online)

Authors: John George Victor, Prof. M Sunil Prakash

Abstract: With the rapid advances in VLSI Technology, design of digital circuits with high speed, low power consumption, high throughput and optimized area is a great challenge for an integrated circuit designer. In Digital design adders are key components, where they perform various functions like addition, subtraction, multiplication and division. Multi-bit width adders are required in Very Large-Scale Integrated circuits (VLSI) for processing of microcontrollers, microprocessors, data processing, Application Specific Integrated Circuits (ASICs) and Digital signal processors. In this Paper various adder cells such as CCMOS, CPL, Hybrid Adder, GDI and proposed GDI full adder cells are analyzed and compared with respect to Delay, Power Dissipation, Power Delay Product and Area. The Gate Diffusion Input (GDI) technique has been used for generation of digital logic functions. This technique is compared with other full adder techniques which allow less power consumption and reduced propagation delay with minimum number of transistors. The speed of the circuit is limited by size of the transistors, parasitic capacitance and delay. An important parameter that evaluates circuit performance is Power Delay Product (PDP) which depends on power consumption and speed. Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Performance is compared by varying power supply voltages. The analysis has been done on the basis of propagation delay, power consumption and power delay product. Reduction in power-delay product is achieved by the proposed GDI technique.