International Journal of Research in Electrical, Electronics and Communication Engineering ISSN: 3107-8907 (Online)

Author: Dr. J. Jasper Gnana Chandran, K. Mathew

Abstract: The aim of the intended work is to design an efficient multiplier architecture based Upon Vertical Horizontal Binary Common Subexpression Elimination (VHBCSE) algorithm for FIR filter synthesis. In any FIR filter, the multiplier is the major constraint which defines the performance of desired filter. Binary Common Subexpression Elimination (BCSE) algorithm introduces the concept of eliminating the Common Subexpression (CS) in binary form for designing an efficient multiplier with low complexity. In VHBCSE, horizontal BCSE algorithm utilizes CSs occurring within each coefficient to get rid of redundant computations, while vertical BCSE uses CSs found across adjacent coefficients to eliminate redundant computations. A 2- bit vertical BCSE has been applied first on the adjacent coefficient, followed by 4 bit and 8 bit horizontal BCSEs to reduce the number of adders required in the multiplier of FIR filters. As a result, the proposed multiplier offers good reduction in the number of adders in realizing FIR filters. The proposed scheme is coded in Verilog language and simulation is performed using Xilinx ISE 13.4.