Recent Trends in Control & Optimization of Power Systems

Authors: Mohammed Waseem Khanooni, S. D. Chede

Abstract: Previously, research and design of Network-on-Chip paradigms where mainly focused on improving the performance of the interconnection networks. With emerging wide range of low-power applications and energy constrained highperformance applications, it is highly desirable to have NoCs that are highly energy efficient without incurring performance penalty. In the design of highperformance massive multi-core chips, power and heat have become dominant constraints. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance and increase cooling costs. Dynamic Voltage Scaling is an efficient technique for significant power savings in microprocessors. It has been proposed and deployed in modern microprocessors by exploiting the variance in processor utilization. On a Network-on-Chip paradigm, it is more likely that the wire line links and buffers are not always fully utilized even for different applications. Hence, by exploiting these characteristics of the links and buffers over different traffic, DVFS technique can be incorporated on these switches and wire line links for huge power savings.