Recent Trends in Electrical Machines and Drives ISSN: 3139-2067 (Online)

A desirable characteristic for display memory compression is support for the raster-scan processing order and the fixed target compression ratio. Set partitioning in hierarchical trees (SPIHT) is an efficient two-dimensional compression algorithm that guarantees a fixed target compression ratio, but its one-dimensional (1D) variation has received little attention, even though its 1D nature supports the raster-scan processing order. This paper proposes a novel hardware design for 1D SPIHT. The algorithm is modified to exploit parallelism for effective hardware implementation. For the encoder, dependences that prohibit parallel execution are resolved and a pipelined schedule is proposed. For the parallel execution of the decoder, the algorithm is modified to enable estimation of the bitstream length of each pass prior to decoding. This modification allows parallel and pipelined decoding operations, leading to a high-throughput design for both encoder and decoder. However, in an actual system, several modules, including the video codec and the external memory, are connected via a system bus. In this environment, the gain in compression and the gain in transfer are very different. For a practical FMC design, not only the compression rate but also the transfer efficiency should be carefully considered. In this paper, a bus-aware interface

design for one dimensional (1D) lossless FMC is proposed to reduce the amount of bus transfers. The proposed bit stream merging and tailed burst length schemes increase the transfer gain such that it is close to the gain in compression. The proposed 1D lossless FMC schemes are implemented in Verilog language and verified in an environment containing a high efficiency video coding (HEVC) encoder and a system bus.

Keywords: Set partitioning in hierarchical trees (SPIHT), one dimensional (1D, high efficiency video coding (HEVC)