FPGA-Based Hardware Acceleration of Image Convolution for Embedded Vision

Abstract

Image convolution is the core operation of embedded vision, underlyingfiltering, edge detection, and the feature extraction of convolutional neuralnetworks, but it is computationally heavy and strains the embedded processors found in cameras and edge devices. A field-programmable gate array can perform the regular, parallel arithmetic of convolution far more efficiently than a general-purpose processor. This paper presents the design and evaluation of a field-programmable gate array accelerator for imageconvolution in embedded vision, in which a pipelined sliding-windowarchitecture processes one pixel per clock cycle. The accelerator wasimplemented on a low-cost system-on-chip field-programmable gate array and compared with an embedded processor across a range of image sizes,measuring execution time, speedup, and power. The accelerator achieved aspeedup of about eight to ten times over the processor, with the advantagegrowing for larger images, while drawing only around two watts. The line-buffer architecture allowed the data to stream through without storing whole images. The results show that a field-programmable gate array provides efficient, low-power acceleration of image convolution for embedded vision. KEYWORDS: FPGA, image convolution, hardware acceleration, embeddedvision, pipelining, parallel processing