In current VLSI technology, high speed devices are employed in many applications, such as dynamic logic circuits, since they outperform static devices in terms of latency, noise immunity, and power consumption. Increased leakage current combined with noise immunity degrades dynamic logic circuit performance.
The body biassed DOIND-ABC2 (DOIND-2) logic is introduced in this study to decrease leakage current with reduced delay cost. In this study, a distinct Active body biassed strategy for DOIND logic approach, termed DOIND- 2(ABC-2), was applied to examine various parameters. The suggested DOIND-2 strategy provides a maximum 70 percent reduction in leakage current when compared to the Domino, DOIND, and DOIND-1 proposed techniques. The proposed DOIND-2 strategy also outperforms all existing approaches in the majority of parameters. The influence of frequency fluctuation in various circuits has been studied in this work. All parameters were tested at the 70 nm technology node with the Tanner EDA tool and a supply voltage of 0.9v.
Keywords: DOIND-2, Valuation, Power dissipation, bias in the active body Domino logic
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