Authors: J. Jagan Pradee, Praveen P N
Abstract: Noise in integrated circuits due to variation in temperature and voltage drop can cause significant variation of performance and also result in functional failure at lower technology nodes. In this paper, we present the proposal for developing an on-chip structure that can
measure the timing uncertainty that is induced by noise in integrated circuits. The noise was induced during test and functional operations to study this. The on-chip structure proposed here helps in speed characterization under different test conditions and workloads. The structure of this chip can be tailored for different applications due to its high scalability. It can find application in monitoring operation condition, silicon validation and validation of
logic built-in-self-test conditions. Results of simulation show that it offers a high measurement resolution and is highly efficient too.
Keywords: Noise, Voltage, Temperature, Measurement, Resolution
Full Issue
| View or download the full issue | PDF 32-44 |