Authors: R. Senthil Kumar, M. Kalaiselvi
Abstract: With the continuous growth in complexity and density of digital integrated circuits, ensuring correctness and reliability has become a critical challenge. Fault modeling and testing play a vital role in identifying manufacturing defects, aging-related failures, and operational faults in digital systems. Effective fault models allow designers to predict faulty behavior, generate test patterns, and evaluate fault coverage systematically. This paper presents a detailed study of fault modeling techniques and digital circuit testing methodologies. Classical and modern fault models such as stuck at, bridging, delay, and transient faults are discussed along with test generation and design-for-testability approaches. Tables and two-dimensional figures are included to support conceptual understanding. The paper serves as a comprehensive reference for students and engineers involved in digital system design and testing.
Keywords: Digital circuit testing, fault modeling, stuck-at faults, delay faults, DFT, fault coverage
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