No 21 (2021)

Design of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog

Authors: Archit Halder, Saurabh Gajanan Bhokare, Dr.Basanta Bhowmik

Abstract: The present study demonstrated the use of various error detection and correction methods that provide a dependable quality of data transmission. Present technological development demands efficient and reliable data transmission systems. During data transmission (from source to destination), the high possibility of erroneous data at the destination (due to the inclusion of noise) is a general phenomenon. Keeping in mind such obstacle present paper addressed one technique to expound the digital design conversion of the Viterbi decoder. The decoder efficaciously exploits the Viterbi algorithm as well as carries out digital design conversion of (2, 1, 4) Convolution Encoder with a constraint length of L=5 and code rate of ½. The design has been verified employing Verilog hardware description language (HDL). Further, synthesis followed by simulation was carried out using XILINX ISE 14.5 simulator.

Keywords: (2,1,4) Convolutional Encoder, Viterbi Decoder, Viterbi algorithm and Trellis structure.

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