No 22 (2021)

Implementation of 128-bit AES Algorithm using Xilinx System Generator

Authors: Atryee Bhuyan, Manisha Das, Abhishek Tamuli, Subham Chakrabarty, Smita Sarma

Abstract: The incredible digital transformation of everyday activities in the Covid-19 pandemic has simultaneously increased the demand for data security and user privacy. Cybersecurity has become a major concern in our country when cashless transactions are at an all-time high along with some other important sectors such as education, work, agriculture, health or entertainment. The cryptographic algorithm known as the “Advanced Encryption Standard (AES)†algorithm is one of the most commonly used symmetric key cryptographic algorithms, where more randomization in secret keys increases the security as well as the complexity of the algorithm. AES is a linear, pipelined and symmetric block cipher where a combination of key generation and S-Box operations make the attackers exhaustive to search for the right one to crack. In this work, a system generator by Xilinx is used to implement 128-bit AES cryptographic algorithm. The synthesis results show the utilization of 121 slice registers and 2.81% LUTs.

Keywords: Bandgap, PTAT, CTAT, opamp. AES (Advanced Encryption Standard), Cryptography, LUT (Look-up Table).

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