Hybrid Graphene–Copper Interconnect Structures for Ultra-HighSpeed Data Paths

Abstract

ABSTRACT: This research introduces a hybrid graphene–copper interconnect topology engineered to reduce resistive losses, lower Joule heating, and enhance highfrequency signal integrity. Graphene layers are embedded along copper lines using a compatible low-temperature transfer process. RF characterization shows substantial improvements in signal attenuation due to graphene’s high carrier mobility and exceptional thermal conductivity. Electromigration tests reveal a 4× lifetime enhancement compared to traditional copper lines, while SPICE-level modeling illustrates a 30% reduction in RC delay. The hybrid approach provides an immediate path for improving performance in high-speed data buses, clock trees, and wide-bandwidth NoC fabrics.

KEYWORDS: Graphene, Copper hybrid, Interconnects, High-speed VLSI, RC delay