High-Reliability Negative-Capacitance Field-Effect Transistor (Ncfet) Logic Using Engineered Ferroelectric Hfzro? Gate Stacks for Energy-Efficient Nano-Cmos Systems

Abstract

ABSTRACT: Negative-Capacitance Field-Effect Transistors (NCFETs) based on ferroelectric hafnium-zirconium oxide (HfZrO? or HZO) have emerged as one of the most promising device technologies for sub-5 nm logic nodes. Their inherent capability to achieve sub-60 mV/decade switching, reduce supply voltage, and boost energy efficiency makes them viable for ultra-low-power computing. However, realizing stable, high-reliability NCFET logic requires carefully engineered ferroelectric layers, robust stack interfaces, and optimized device-to-circuit co-design. This paper presents a comprehensive review of high-reliability NCFET logic using HfZrO?-based gate stacks. It highlights material properties, device physics, reliability barriers, fabrication strategies, logic-level design considerations, and future opportunities. The study also addresses challenges related to ferroelectric wake-up, fatigue, imprint, domain dynamics, and cycle-to-cycle variability. The scope of the work extends to energy-efficient digital logic, next-generation microprocessors, AI accelerators, and near-threshold operation. This paper aims to serve as a technically detailed and cohesive resource for researchers exploring reliable ferroelectric-enhanced transistors for future CMOS scaling.

KEYWORDS: NCFET, HfZrO? ferroelectric, negative capacitance, reliability, low-power logic