Architecture-Level Optimization Of 3d Tsv-Based Multicore Systems

Abstract

ABSTRACT: Three-dimensional stacked architectures using through-silicon vias (TSVs) are crucial for enhancing bandwidth, reducing interconnect lengths, and improving energy efficiency in multicore processors. This paper presents a novel optimization framework addressing TSV placement, thermal planning, and inter-tier communication scheduling. A hierarchical thermal-electrical cosimulation method evaluates hotspots, signal integrity, and latency across tiers. Experimental results on synthetic and real workloads show that optimized TSV distribution can reduce peak temperature by 11°C and improve total system throughput by up to 22%. Additionally, an adaptive inter-tier routing mechanism minimizes buffer overhead and dynamic energy consumption. These results advocate for design-automation methodologies tailored to dense 3D VLSI systems.

KEYWORDS: 3D integration, TSV, Multicore processors, Thermal analysis, System architecture