Analog-Aware Floorplanning for Mixed-Signal Nano-Cmos Socs

Abstract

ABSTRACT: As technology nodes shrink, mixed-signal SoCs face increased challenges in noise coupling, substrate interference, and analog-digital cohabitation. This paper presents an analog-aware floorplanning methodology incorporating shielding, isolation, and adaptive well engineering to minimize cross-domain interference. Using a 28 nm test chip with RF, sensor, and digital control blocks, the framework reduces analog noise by 37% and improves ADC performance by 1.8 ENOB. The study also includes a predictive model correlating physical layout parameters with analog degradation metrics. These results show the importance of geometry-driven analog-aware design in modern SoCs.

KEYWORDS: Mixed-signal SoC, Floorplanning, Substrate noise, NanoCMOS, Isolation